Aaron Durbin b37d1fb95a lynxpoint: update MBP give up routine ...

I'm not sure if I screwed this up originally or the Intel docs changed
(I didn't bother to go back and check). According to ME BWG 1.1.0 the give
up bit is in the host general status #2 register.

Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2808
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2013-03-21 23:03:27 +01:00

..

arch

coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE

2013-03-21 22:28:28 +01:00

console

Fix race condition building console code

2013-03-21 22:08:05 +01:00

cpu

haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option

2013-03-21 23:02:31 +01:00

device

ramstage: prepare for relocation

2013-03-21 18:01:38 +01:00

drivers

GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«

2013-03-01 10:16:08 +01:00

ec

Support ITE IT8518 embedded controller running Quanta's firmware

2013-03-14 04:54:21 +01:00

include

coreboot: add caching loaded ramstage interface

2013-03-21 22:59:40 +01:00

lib

coreboot: add caching loaded ramstage interface

2013-03-21 22:59:40 +01:00

mainboard

Supermicro H8SCM: Use SPD read code from F15 wrapper

2013-03-20 05:54:51 +01:00

northbridge

haswell: add multipurpose SMM memory region

2013-03-21 22:59:03 +01:00

southbridge

lynxpoint: update MBP give up routine

2013-03-21 23:03:27 +01:00

superio

Super I/O W83627DHG: Enable UART B by redirecting pins

2013-03-15 17:51:48 +01:00

vendorcode

f15tn/Include/OptionIdsInstall.h: Remove idle … || )

2013-03-20 17:50:02 +01:00

Kconfig

coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE

2013-03-21 22:28:28 +01:00