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https://github.com/Telecominfraproject/OpenCellular.git
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edbfb3a43b
Add support to enable the architectural D-cache on ARMv7-M CPU supporting it. Update the MPU code in order to be able to declare an 'uncached' RAM region (e.g. to store the DMA buffer). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=with the following CL, on ZerbleBarn, boot and capture a finger image. Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285 Reviewed-on: https://chromium-review.googlesource.com/1032776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
77 lines
1.9 KiB
ArmAsm
77 lines
1.9 KiB
ArmAsm
/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* ARMv7-M architectural caches maintenance operations.
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*/
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.syntax unified
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.text
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.thumb
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/* System Control Block: cache registers */
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#define SCB_CCSIDR 0xe000ed80
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#define SCB_CCSELR 0xe000ed84
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#define SCB_DCISW 0xe000ef60
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#define SCB_DCCISW 0xe000ef74
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.macro dcache_set_way_op name register
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@
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@ Perform an operation on all D-cache sets/ways.
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@
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@ Note: implemented in assembly to guarantee that we are not touching the
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@ D-cache in the middle of the loop.
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@
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.thumb_func
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.section .text.\name
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.global \name
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\name:
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/* Select Level-1 Data cache (for operations on CCSIDR). */
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ldr r1, =SCB_CCSELR
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movs r0, #0
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ldr r2, =SCB_CCSIDR
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str r0, [r1] /* set CCSELR = 0 */
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/* Ensure the CCSELR write is effective before reading CCSIDR. */
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dsb
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/* CCSIDR contains the cache geometry. */
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ldr r3, [r2] /* [27:13] Number of sets -1 [12:3] Number of ways -1 */
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/* register used to do the set/way cache operation. */
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ldr r0, =\register
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/* r2 is the number of cache 'sets' - 1 */
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ubfx r2, r3, #13, #15
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/* r12 is the number of cache 'ways' - 1 */
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ubfx r12, r3, #3, #10
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1:
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mov r1, r12 /* reset way index */
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2:
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/*
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* Build address Set/Way operation e.g DC(C)ISW
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* [31:30] way index [13:5] set index
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*/
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lsls r3, r2, #5 /* set index */
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/* TODO(crbug.com/848704) remove cache geometry assumptions */
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orr r3, r3, r1, lsl #30 /* way index */
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/* Perform operation (e.g invalidate) on a D-cache line */
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str r3, [r0]
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/* go to previous way */
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subs r1, #1
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bcs 2b
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/* go to previous set */
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subs r2, #1
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bcs 1b
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/* Ensure everything has propagated and return. */
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dsb
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isb
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bx lr
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.endm
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/* D-cache Invalidate by set-way */
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dcache_set_way_op cpu_invalidate_dcache SCB_DCISW
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/* D-cache Clean and Invalidate by set-way, to Point of Coherency */
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dcache_set_way_op cpu_clean_invalidate_dcache SCB_DCCISW
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