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OpenCellular/src
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Edward O'Callaghan dfa8a32f1f src/mainboard/asrock/e350m1: Properly indent devicetree.cb 
Trivial: clean up spaces to tabs to properly indent devicetree.cb

Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29 20:54:03 +02:00
..
arch
Rename coreboot_ram stage to ramstage
2014-04-26 13:27:09 +02:00
console
console: Simplify the enable rules
2014-04-18 16:41:09 +02:00
cpu
AGESA SPI: Fix Kconfig options
2014-04-29 17:31:40 +02:00
device
OxPCIe uart: Split PCI bridge control
2014-04-09 11:29:45 +02:00
drivers
SPI: Use common dependency in Kconfig
2014-04-29 17:31:03 +02:00
ec
ec/compal/ene932: Update to use coreboot EC-mainboard API
2014-04-19 03:49:48 +02:00
include
AMD: Add common header file for CAR setup
2014-04-28 18:36:35 +02:00
lib
Rename coreboot_ram stage to ramstage
2014-04-26 13:27:09 +02:00
mainboard
src/mainboard/asrock/e350m1: Properly indent devicetree.cb
2014-04-29 20:54:03 +02:00
northbridge
Rename coreboot_ram stage to ramstage
2014-04-26 13:27:09 +02:00
soc
console: Move newline translation outside console_tx_byte
2014-04-09 13:21:25 +02:00
southbridge
AGESA SPI: Fix Kconfig options
2014-04-29 17:31:40 +02:00
superio
superio/winbond/w83627ehg: Convert romstage to generic component
2014-04-28 20:14:58 +02:00
vendorcode
vendorcode/amd/agesa/fam14: Build as a static library
2014-04-15 17:23:37 +02:00
Kconfig
Rename coreboot_ram stage to ramstage
2014-04-26 13:27:09 +02:00