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Previously, sleep was being reenabled only after tpm fifo reads as that would typcially be near the end of a host driven TPM command. However, in the case the host reads or writes to the STS register, then sleep would not be re-enabled. Moved the re-enable point to at the end of every i2cs interrupt. Since sleep is delayed by 1 second prior to being reenabled then Cr50 will not go to sleep in the middle of TPM command since the host is either writing or reading STS at a much faster rate when a TPM command is being executed. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Added a debug counter in idle.c and shortened sleep delays from 3 minutes to 5 seconds. Unplugged suzyq and verified that when reconnected, the counter was incrementing to verify that Reef would go to sleep. Also verified that TPM worked successfully and kernel was launched. Change-Id: I03ad33ed3591bbba24b5c56445c06d0e11368019 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/401808 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>