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https://github.com/Telecominfraproject/OpenCellular.git
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5b71b33aba
Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Glower board configuration */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/* Optional features */
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/* #define CONFIG_BACKLIGHT_LID */
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/* #define CONFIG_BATTERY_SMART */
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#define CONFIG_BOARD_VERSION
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#define CONFIG_PORT80_TASK_EN
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#if 0
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#define CONFIG_CHARGER
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#define CONFIG_CHARGER_V1
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#define CONFIG_CHARGER_BQ24715
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#define CONFIG_CHARGER_DISCHARGE_ON_AC
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#define CONFIG_CHARGER_INPUT_CURRENT 1700 /* 33 W adapter, 19 V, 1.75 A */
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#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
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#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input senso resistor, mOhm */
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#endif
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#define CONFIG_CHIPSET_BAYTRAIL
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#define CONFIG_CHIPSET_CAN_THROTTLE
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#define CONFIG_POWER_COMMON
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#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
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/* #define CONFIG_CMD_GSV */
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#define CONFIG_EXTPOWER_GPIO
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#define CONFIG_I2C_PASSTHRU_RESTRICTED
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#define CONFIG_KEYBOARD_COL2_INVERTED
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#define CONFIG_KEYBOARD_IRQ_GPIO GPIO_KBD_IRQ_L
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#define CONFIG_KEYBOARD_PROTOCOL_8042
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/* #define CONFIG_LED_COMMON */
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#define CONFIG_POWER_BUTTON
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#define CONFIG_POWER_BUTTON_X86
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#define CONFIG_USB_PORT_POWER_IN_S3
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#define CONFIG_USB_PORT_POWER_SMART
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#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
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/* #define CONFIG_VBOOT_HASH */
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/*
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#define CONFIG_WIRELESS
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#define CONFIG_WIRELESS_SUSPEND \
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(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
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*/
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#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
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#define CONFIG_WATCHDOG_HELP
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#define CONFIG_CLOCK_CRYSTAL
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/* 512kb SPI flash */
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#define CONFIG_SPI_FLASH_SIZE 0x00080000
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#define CONFIG_SPI_FLASH_W25X40
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#define CONFIG_SPI_FLASH_PORT 1
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SPI_FLASH
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#undef CONFIG_TASK_PROFILING
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/* Modules we want to exclude */
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#undef CONFIG_ADC
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#undef CONFIG_EEPROM
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#undef CONFIG_EOPTION
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#undef CONFIG_PECI
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#undef CONFIG_PSTORE
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#undef CONFIG_PWM
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#ifndef __ASSEMBLER__
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/* I2C ports */
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#define I2C_PORT_BATTERY MEC1322_I2C1
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#define I2C_PORT_CHARGER MEC1322_I2C1
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#define I2C_PORT_THERMAL MEC1322_I2C2
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/* USB ports */
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#define USB_PORT_COUNT 2
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/* Wireless signals */
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#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
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#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
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#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
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#include "gpio_signal.h"
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/* power signal definitions */
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enum power_signal {
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X86_PGOOD_PP1050 = 0,
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X86_PGOOD_PP3300_PCH,
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X86_PGOOD_PP5000,
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X86_PGOOD_S5,
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X86_PGOOD_VCORE,
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X86_PGOOD_PP1000_S0IX,
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X86_SLP_S3_DEASSERTED,
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X86_SLP_S4_DEASSERTED,
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#ifdef CONFIG_CHIPSET_DEBUG
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X86_SLP_SX_DEASSERTED,
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X86_SUS_STAT_ASSERTED,
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X86_SUSPWRDNACK_ASSERTED,
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#endif
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/* Number of X86 signals */
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POWER_SIGNAL_COUNT
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};
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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