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571b7bb640
This patch syncs up TPM2 sources into the build area when building
cr50 image. This relies on a specific directory layout so that the ec
makefile has access to the tpm2 source tree.
The sources are copied using rsync, the tpm2 library is a dependency
for the RO/RW elf images, and is declared to be a phony make target,
which guarantees that the tpm2 make is always run when cr50 image is
built.
Include files in board/cr50/tpm2 are necessary to be able to build
tpm2 code using the bare metal toolchain used for building ec code.
memory.h is in fact empty, it is easier to add it here than to wrap it
in conditional compilation at the source.
Make variables CROSS_COMPILE and CFLAGS are exported for the benefit
of the tpm2 makefile. ROOTDIR indicates where tpm2 library should look
for .h files not available from the toolchain.
CQ-DEPEND=CL:292946
BRANCH=none
BUG=chrome-os-partner:43025
TEST=make buildall -j succeeds;
when linked with the latest tpm2 source, the combined image
starts the tmp task and reacts to the host sending the startup
command (failing due to unplugged stubs).
Change-Id: Ia3fd260588558c2bacd724df9583052fa4660ca3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292975
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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#include "core/cortex-m/config_core.h"
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/* Number of IRQ vectors on the NVIC */
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/* TODO_FPGA this should come from the generated .h file */
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#define CONFIG_IRQ_COUNT 188
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/* Describe the RAM layout */
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#define CONFIG_RAM_BASE 0x10000
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#define CONFIG_RAM_SIZE 0x10000
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/* Flash chip specifics */
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/* TODO(crosbug.com/p/33815): These are probably wrong. Don't use them yet. */
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#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
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#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
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/* Describe the flash layout */
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#define CONFIG_FLASH_BASE 0x40000
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/* TODO(wfrichar): Lying about this, so image signing works.
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* I'll file a bug once this CL goes in. */
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/* #define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024) */
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#define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024)
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/* Compute the rest of the flash params from these */
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#include "config_std_internal_flash.h"
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 500
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* Idle task stack size */
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#define IDLE_TASK_STACK_SIZE 256
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/* Default task stack size */
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#define TASK_STACK_SIZE 488
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/* Larger task stack size, for hook task */
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#define LARGER_TASK_STACK_SIZE 640
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/* Maximum number of deferrable functions */
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#define DEFERRABLE_MAX_COUNT 8
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#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
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#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask)
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/* TODO_FPGA this should come from the generated .h file */
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#define PCLK_FREQ (24 * 1000 * 1000)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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