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1b53f74664
The new FPGA version adds a lot of few features, while temporarily
cutting off some existing capabilities like clocking configuration
(hardwared clocks used instead), pinmux assignment for SPS interface
(hardwared connections used), etc.
This patch removes some now unused code, modifies some configuration
items and adds TODO_FGPA comment blocks highlighting code which needs
to be reviews next time FPGA version changes).
The new register definitions file is derived from hardware
description.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=with these changes in place the B1 board boots to the console
prompt.
Change-Id: I78ec6b2831a44cbfd40ee726a5d3c2cc11bf2cfa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291855
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Watchdog driver */
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#include "common.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "util.h"
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#include "watchdog.h"
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/* magic value to unlock the watchdog registers */
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#define WATCHDOG_MAGIC_WORD 0x1ACCE551
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/* Watchdog expiration : assume 30 Mhz clock for now */
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#define WATCHDOG_PERIOD (CONFIG_WATCHDOG_PERIOD_MS * (30000000 / 1000))
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/* Warning interrupt at the middle of the watchdog period */
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void IRQ_HANDLER(GC_IRQNUM_WATCHDOG0_WDOGINT)(void) __attribute__((naked));
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void IRQ_HANDLER(GC_IRQNUM_WATCHDOG0_WDOGINT)(void)
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{
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/* Naked call so we can extract raw LR and SP */
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asm volatile("mov r0, lr\n"
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"mov r1, sp\n"
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/* Must push registers in pairs to keep 64-bit aligned
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* stack for ARM EABI. This also conveninently saves
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* R0=LR so we can pass it to task_resched_if_needed. */
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"push {r0, lr}\n"
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"bl watchdog_trace\n"
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/* Do NOT reset the watchdog interrupt here; it will
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* be done in watchdog_reload(), or reset will be
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* triggered if we don't call that by the next watchdog
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* period. Instead, de-activate the interrupt in the
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* NVIC, so the watchdog trace will only be printed
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* once.
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*/
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"mov r0, %[irq]\n"
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"bl task_disable_irq\n"
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"pop {r0, lr}\n"
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"b task_resched_if_needed\n"
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: : [irq] "i" (GC_IRQNUM_WATCHDOG0_WDOGINT));
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}
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const struct irq_priority IRQ_PRIORITY(GC_IRQNUM_WATCHDOG0_WDOGINT)
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__attribute__((section(".rodata.irqprio")))
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= {GC_IRQNUM_WATCHDOG0_WDOGINT, 0};
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/* put the watchdog at the highest priority */
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void watchdog_reload(void)
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{
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uint32_t status = GR_WATCHDOG_RIS;
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/* Unlock watchdog registers */
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GR_WATCHDOG_LOCK = WATCHDOG_MAGIC_WORD;
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/* As we reboot only on the second timeout, if we have already reached
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* the first timeout we need to reset the interrupt bit. */
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if (status) {
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GR_WATCHDOG_ICR = status;
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/* That doesn't seem to unpend the watchdog interrupt (even if
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* we do dummy writes to force the write to be committed), so
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* explicitly unpend the interrupt before re-enabling it. */
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task_clear_pending_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
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task_enable_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
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}
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/* Reload the watchdog counter */
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GR_WATCHDOG_LOAD = WATCHDOG_PERIOD;
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/* Re-lock watchdog registers */
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GR_WATCHDOG_LOCK = 0xdeaddead;
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}
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DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
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int watchdog_init(void)
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{
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/* Enable clocks */
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/* TODO_FPGA add relevant clock init here, when supported. */
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/* Unlock watchdog registers */
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GR_WATCHDOG_LOCK = WATCHDOG_MAGIC_WORD;
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/* Reload the watchdog counter */
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GR_WATCHDOG_LOAD = WATCHDOG_PERIOD;
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/* Reset after 2 time-out : activate both interrupt and reset. */
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GR_WATCHDOG_CTL = 0x3;
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/* Reset watchdog interrupt bits */
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GR_WATCHDOG_ICR = GR_WATCHDOG_RIS;
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/* Lock watchdog registers against unintended accesses */
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GR_WATCHDOG_LOCK = 0xdeaddead;
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/* Enable watchdog interrupt */
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task_enable_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
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return EC_SUCCESS;
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}
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