mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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Added common priority for the ADC init to ensure board level priority is defined for the ADC pre init. BUG=none TEST=make buildall -j BRANCH=none Change-Id: Id1649df6a68ab53bd110e58a0722bd4c70cbffc5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/286040 Reviewed-by: Shawn N <shawnn@chromium.org>
172 lines
4.4 KiB
C
172 lines
4.4 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* IT8380 ADC module for Chrome EC */
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#include "adc.h"
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#include "adc_chip.h"
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#include "clock.h"
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#include "console.h"
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#include "common.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Data structure of ADC channel control registers. */
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const struct adc_ctrl_t adc_ctrl_regs[] = {
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{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL,
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&IT83XX_GPIO_GPCRI0},
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{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL,
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&IT83XX_GPIO_GPCRI1},
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{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL,
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&IT83XX_GPIO_GPCRI2},
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{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL,
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&IT83XX_GPIO_GPCRI3},
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{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL,
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&IT83XX_GPIO_GPCRI4},
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{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL,
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&IT83XX_GPIO_GPCRI5},
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{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL,
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&IT83XX_GPIO_GPCRI6},
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{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL,
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&IT83XX_GPIO_GPCRI7},
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};
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static void adc_enable_channel(int ch)
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{
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if (ch < 4)
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/*
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* for channel 0, 1, 2, and 3
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* bit4 ~ bit0 : indicates voltage channel[x]
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* input is selected for measurement (enable)
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* bit 7 : W/C data valid flag
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*/
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*adc_ctrl_regs[ch].adc_ctrl = 0x80 + ch;
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else
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/*
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* for channel 4, 5, 6, and 7
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* bit4 : voltage channel enable (ch 4~7 only)
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* bit7 : W/C data valid flag
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*/
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*adc_ctrl_regs[ch].adc_ctrl = 0x90;
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/* bit 0 : adc module enable */
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IT83XX_ADC_ADCCFG |= 0x01;
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}
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static void adc_disable_channel(int ch)
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{
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if (ch < 4)
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/*
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* for channel 0, 1, 2, and 3
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* bit4 ~ bit0 : indicates voltage channel[x]
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* input is selected for measurement (disable)
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* bit 7 : W/C data valid flag
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*/
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*adc_ctrl_regs[ch].adc_ctrl = 0x9F;
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else
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/*
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* for channel 4, 5, 6, and 7
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* bit4 : voltage channel disable (ch 4~7 only)
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* bit7 : W/C data valid flag
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*/
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*adc_ctrl_regs[ch].adc_ctrl = 0x80;
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/* bit 0 : adc module disable */
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IT83XX_ADC_ADCCFG &= ~0x01;
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}
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int adc_read_channel(enum adc_channel ch)
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{
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/* voltage 0 ~ 3v = adc data register raw data 0 ~ 3FFh (10-bit ) */
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uint16_t adc_raw_data;
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int num;
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int adc_ch;
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adc_ch = adc_channels[ch].channel;
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adc_enable_channel(adc_ch);
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/* Maximum time for waiting ADC conversion is ~1.525ms */
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for (num = 0x00; num < 100; num++) {
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/* delay ~15.25us */
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IT83XX_GCTRL_WNCKR = 0;
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/* data valid of adc channel[x] */
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if (IT83XX_ADC_ADCDVSTS & (1 << adc_ch)) {
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/* read adc raw data msb and lsb */
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adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
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*adc_ctrl_regs[adc_ch].adc_datl;
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/* W/C data valid flag */
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IT83XX_ADC_ADCDVSTS = (1 << adc_ch);
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adc_disable_channel(adc_ch);
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return adc_raw_data * adc_channels[ch].factor_mul /
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adc_channels[ch].factor_div +
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adc_channels[ch].shift;
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}
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}
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adc_disable_channel(adc_ch);
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return ADC_READ_ERROR;
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}
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int adc_read_all_channels(int *data)
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{
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int index;
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for (index = 0; index < ADC_CH_COUNT; index++) {
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data[index] = adc_read_channel(index);
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if (data[index] == ADC_READ_ERROR)
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return EC_ERROR_UNKNOWN;
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}
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return EC_SUCCESS;
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}
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/*
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* ADC analog accuracy initialization (only once after VSTBY power on)
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*
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* Write 1 to this bit and write 0 to this bit immediately once and
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* only once during the firmware initialization and do not write 1 again
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* after initialization since IT8380 takes much power consumption
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* if this bit is set as 1
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*/
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static void adc_accuracy_initialization(void)
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{
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/* bit3 : start adc accuracy initialization */
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IT83XX_ADC_ADCSTS |= 0x08;
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/* short delay for adc accuracy initialization */
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IT83XX_GCTRL_WNCKR = 0;
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/* bit3 : stop adc accuracy initialization */
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IT83XX_ADC_ADCSTS &= ~0x08;
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}
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/* ADC module Initialization */
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static void adc_init(void)
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{
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int index;
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int ch;
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/* ADC analog accuracy initialization */
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adc_accuracy_initialization();
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for (index = 0; index < ADC_CH_COUNT; index++) {
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ch = adc_channels[index].channel;
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/* enable adc channel[x] function pin */
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*adc_ctrl_regs[ch].adc_pin_ctrl = 0x00;
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}
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/* bit 5 : ADCCTS0 = 1 */
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IT83XX_ADC_ADCCFG = 0x20;
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IT83XX_ADC_ADCCTL = 0x04;
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}
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DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
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