mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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ffac23c0ea
Our code base contains a lot of debug messages in this pattern:
CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n")
The strings are taking up spaces in the EC binaries, so let's refactor
this by adding cprints() and ccprints().
cprints() is just like cprintf(), except that it adds the brackets
and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...)
This saves us hundreds of bytes in EC binaries.
BUG=chromium:374575
TEST=Build and check flash size
BRANCH=None
Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200490
Reviewed-by: Randall Spangler <rspangler@chromium.org>
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Clocks and power management settings */
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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/* Console output macros. */
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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static int freq;
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struct clock_gate_ctrl {
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volatile uint8_t *reg;
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uint8_t mask;
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};
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void clock_init(void)
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{
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#if PLL_CLOCK == 48000000
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/* Set PLL frequency to 48MHz. */
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IT83XX_ECPM_PLLFREQR = 0x04;
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freq = PLL_CLOCK;
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#else
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#error "Support only for PLL clock speed of 48MHz."
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#endif
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/* Set EC Clock Frequency to PLL frequency. */
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IT83XX_ECPM_SCDCR3 &= 0xf0;
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/*
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* The VCC power status is treated as power-on.
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* The VCC supply of LPC and related functions (EC2I,
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* KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI).
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* It means VCC (pin 11) should be logic high before using
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* these functions, or firmware treats VCC logic high
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* as following setting.
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*/
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IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
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/* Turn off auto clock gating. */
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IT83XX_ECPM_AUTOCG = 0x00;
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}
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int clock_get_freq(void)
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{
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return freq;
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}
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/**
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* Enable clock to specified peripheral
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*
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* @param offset Should be element of clock_gate_offsets enum.
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* Bits 8-15 specify the ECPM offset of the specific clock reg.
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* Bits 0-7 specify the mask for the clock register.
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* @param mask Unused
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* @param mode Unused
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*/
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void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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volatile uint8_t *reg = (volatile uint8_t *)
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(IT83XX_ECPM_BASE + (offset >> 8));
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uint8_t reg_mask = offset & 0xff;
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/*
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* Note: CGCTRL3R, bit 6, must always write 1, but since there is no
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* offset argument that addresses this bit, then we are guaranteed
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* that this line will write a 1 to that bit.
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*/
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*reg &= ~reg_mask;
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}
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/**
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* Disable clock to specified peripheral
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*
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* @param offset Should be element of clock_gate_offsets enum.
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* Bits 8-15 specify the ECPM offset of the specific clock reg.
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* Bits 0-7 specify the mask for the clock register.
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* @param mask Unused
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* @param mode Unused
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*/
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void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
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{
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volatile uint8_t *reg = (volatile uint8_t *)
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(IT83XX_ECPM_BASE + (offset >> 8));
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uint8_t reg_mask = offset & 0xff;
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uint8_t tmp_mask = 0;
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/* CGCTRL3R, bit 6, must always write a 1. */
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tmp_mask |= ((offset >> 8) == IT83XX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00;
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*reg |= reg_mask | tmp_mask;
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}
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