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7aab81edce
When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
109 lines
2.4 KiB
C
109 lines
2.4 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver */
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#include "clock.h"
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#include "common.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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void __hw_clock_event_set(uint32_t deadline)
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{
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/* set the match on the deadline */
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LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
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/* Set the match interrupt */
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LM4_TIMER_IMR(6) |= 0x10;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return 0xffffffff - LM4_TIMER_TAMATCHR(6);
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}
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void __hw_clock_event_clear(void)
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{
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/* Disable the match interrupt */
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LM4_TIMER_IMR(6) &= ~0x10;
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}
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uint32_t __hw_clock_source_read(void)
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{
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return 0xffffffff - LM4_TIMER_TAV(6);
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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LM4_TIMER_TAV(6) = 0xffffffff - ts;
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}
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void __hw_clock_source_irq(void)
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{
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uint32_t status = LM4_TIMER_RIS(6);
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/* Clear interrupt */
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LM4_TIMER_ICR(6) = status;
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/*
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* Find expired timers and set the new timer deadline; check the IRQ
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* status to determine if the free-running counter overflowed.
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*/
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process_timers(status & 0x01);
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}
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DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
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static void update_prescaler(void)
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{
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/*
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* Set the prescaler to increment every microsecond. This takes
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* effect immediately, because the TAILD bit in TAMR is clear.
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*/
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LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
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int __hw_clock_source_init(uint32_t start_t)
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{
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/*
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* Use WTIMER0 (timer 6) configured as a free running counter with 1 us
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* period.
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*/
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/* Enable WTIMER0 clock in run and sleep modes. */
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clock_enable_peripheral(CGC_OFFSET_WTIMER, 0x1,
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CGC_MODE_RUN | CGC_MODE_SLEEP);
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/* Ensure timer is disabled : TAEN = TBEN = 0 */
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LM4_TIMER_CTL(6) &= ~0x101;
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/* Set overflow interrupt */
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LM4_TIMER_IMR(6) = 0x1;
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/* 32-bit timer mode */
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LM4_TIMER_CFG(6) = 4;
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/* Set initial prescaler */
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update_prescaler();
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/* Periodic mode, counting down */
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LM4_TIMER_TAMR(6) = 0x22;
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/* Use the full 32-bits of the timer */
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LM4_TIMER_TAILR(6) = 0xffffffff;
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/* Starts counting in timer A */
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LM4_TIMER_CTL(6) |= 0x1;
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/*
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* Override the count with the start value now that counting has
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* started.
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*/
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__hw_clock_source_set(start_t);
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/* Enable interrupt */
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task_enable_irq(LM4_IRQ_TIMERW0A);
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return LM4_IRQ_TIMERW0A;
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}
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