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957638c78c
Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
34 lines
1.3 KiB
C
34 lines
1.3 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* NPCX-specific SIB module for Chrome EC */
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#ifndef __CROS_EC_SYSTEM_CHIP_H
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#define __CROS_EC_SYSTEM_CHIP_H
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/* Indices for battery-backed ram (BBRAM) data position */
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enum bbram_data_index {
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BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
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BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
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BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */
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BBRM_DATA_INDEX_PBUTTON = 12, /* Power button for hibernate */
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BBRM_DATA_INDEX_VBNVCNTXT = 16, /* VbNvContext for ARM arch */
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BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */
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};
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/* Issue a watchdog reset*/
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void system_watchdog_reset(void);
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/* Check reset cause and return reset flags */
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void system_check_reset_cause(void);
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/* End address for the .lpram section; defined in linker script */
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extern unsigned int __lpram_fw_end;
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/* Begin flash address for the lpram codes; defined in linker script */
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extern unsigned int __flash_lpfw_start;
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/* End flash address for the lpram codes; defined in linker script */
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extern unsigned int __flash_lpfw_end;
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#endif /* __CROS_EC_SYSTEM_CHIP_H */
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