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16eaf5cfde
The check for overflow was originally in __hw_clock_source_read() If it got interrupted, it would frequently see an overflow, because "prev_read" would be less than "now". 1 - Use the comparator to check for overflow. 2 - Only check for overflow in the interrupt handler. BUG=chrome-os-partner:35312 BRANCH=none TEST=make buildall -j use the keyboard code to type use a console command "forcetime", to force the system time to overflow soon. Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I7005724222289ba967e89af0ce8b9ef8f90a4ae4 Reviewed-on: https://chromium-review.googlesource.com/239967 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Myles Watson <mylesgw@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
164 lines
4.2 KiB
C
164 lines
4.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/*
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* Hardware timers driver.
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*
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* nRF51x has one hardware counter, but 4 stand-alone capture/compare (CC)
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* registers.
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*
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* CC(0) -- used to interrupt next clock event.
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* CC(1) -- used to capture the current value.
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* CC(2) -- used to detect overflow on virtual timer (not hardware).
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*/
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#include "common.h"
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#include "console.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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static uint32_t last_deadline; /* cache of event set */
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/*
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* The nRF51x timer cannot be set to a specified value (reset to zero only).
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* Thus, we have to use a variable "shift" to maintain the offset between the
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* hardware value and virtual clock value.
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*
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* Once __hw_clock_source_set(ts) is called, the shift will be like:
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*
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* virtual time ------------------------------------------------
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* <----------> ^
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* shift | ts
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* 0 | |
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* hardware v
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* counter time ------------------------------------------------
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*
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*
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* Below diagram shows what it is when overflow happens.
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*
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* | now | prev_read
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* v v
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* virtual time ------------------------------------------------
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* ----> <------
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* shift shift
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* |
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* hardware v
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* counter time ------------------------------------------------
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*
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*/
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static uint32_t shift;
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void __hw_clock_event_set(uint32_t deadline)
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{
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last_deadline = deadline;
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NRF51_TIMER0_CC0 = deadline - shift;
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/* enable interrupt */
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NRF51_TIMER0_INTENSET = 1 << NRF51_TIMER_COMPARE0_BIT;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return last_deadline;
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}
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void __hw_clock_event_clear(void)
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{
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/* disable interrupt */
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NRF51_TIMER0_INTENCLR = 1 << NRF51_TIMER_COMPARE0_BIT;
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}
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uint32_t __hw_clock_source_read(void)
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{
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/* to capture the current value */
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NRF51_TIMER0_CAPTURE1 = 1;
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return NRF51_TIMER0_CC1 + shift;
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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shift = ts;
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/* reset counter to zero */
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NRF51_TIMER0_STOP = 1;
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NRF51_TIMER0_CLEAR = 1;
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/* So that no interrupt until next __hw_clock_event_set() */
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NRF51_TIMER0_CC0 = ts - 1;
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/* Update the overflow point */
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NRF51_TIMER0_CC2 = 0 - shift;
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/* Start the timer again */
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NRF51_TIMER0_START = 1;
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}
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/* Interrupt handler for timer */
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void timer_irq(void)
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{
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int overflow = 0;
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/* clear status */
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NRF51_TIMER0_COMPARE0 = 0;
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if (NRF51_TIMER0_COMPARE2) {
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NRF51_TIMER0_COMPARE2 = 0;
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overflow = 1;
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}
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process_timers(overflow);
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}
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DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1);
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int __hw_clock_source_init(uint32_t start_t)
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{
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/* Start the high freq crystal oscillator */
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NRF51_CLOCK_HFCLKSTART = 1;
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/* TODO: check if the crystal oscillator is running (HFCLKSTAT) */
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/* 32-bit timer mode */
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NRF51_TIMER0_MODE = NRF51_TIMER0_MODE_TIMER;
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NRF51_TIMER0_BITMODE = NRF51_TIMER0_BITMODE_32;
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/*
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* The external crystal oscillator is 16MHz (HFCLK).
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* Set the prescaler to 16 so that the timer counter is increasing
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* every micro-second (us).
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*/
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NRF51_TIMER0_PRESCALER = 4; /* actual value is 2**4 = 16 */
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/* Not to trigger interrupt until __hw_clock_event_set() is called. */
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NRF51_TIMER0_CC0 = 0xffffffff;
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/* Set to 0 so that the next overflow can trigger timer_irq(). */
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NRF51_TIMER0_CC2 = 0;
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NRF51_TIMER0_INTENSET = 1 << NRF51_TIMER_COMPARE2_BIT;
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/* Clear the timer counter */
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NRF51_TIMER0_CLEAR = 1;
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/* Override the count with the start value now that counting has
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* started. */
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__hw_clock_source_set(start_t);
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/* Enable interrupt */
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task_enable_irq(NRF51_PERID_TIMER0);
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/* Start the timer */
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NRF51_TIMER0_START = 1;
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return NRF51_PERID_TIMER0;
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}
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