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https://github.com/Telecominfraproject/OpenCellular.git
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014d180b1d
The USART peripheral in the L and F families is different enough to need different receive drivers. In particular, the L family USART perihperal has no way of disabling the overflow error bit. So for that family we check and clear the bit, and keep a count of overflows. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Iea26c242d5177afd552a3bd4d6ab1a9c7a65f90e Reviewed-on: https://chromium-review.googlesource.com/288978 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
59 lines
2.0 KiB
Makefile
59 lines
2.0 KiB
Makefile
# -*- makefile -*-
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# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# STM32 chip specific files build
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#
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ifeq ($(CHIP_FAMILY),stm32f0)
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# STM32F0xx sub-family has a Cortex-M0 ARM core
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CORE:=cortex-m0
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# Force ARMv6-M ISA used by the Cortex-M0
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CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0
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else ifeq ($(CHIP_FAMILY),stm32f3)
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# STM32F3xx sub-family has a Cortex-M4 ARM core
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CORE:=cortex-m
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# Allow the full Cortex-M4 instruction set
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CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
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else
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# other STM32 SoCs have a Cortex-M3 ARM core
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CORE:=cortex-m
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# Force Cortex-M3 subset of instructions
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CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
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endif
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# Select between 16-bit and 32-bit timer for clock source
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TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,)
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chip-y=dma.o
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chip-$(CONFIG_COMMON_RUNTIME)+=system.o
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chip-y+=jtag-$(CHIP_FAMILY).o clock-$(CHIP_FAMILY).o
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chip-$(CONFIG_SPI)+=spi.o
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chip-$(CONFIG_SPI_MASTER)+=spi_master.o
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chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o
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chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o
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chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o
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chip-$(CONFIG_STREAM_USART)+=usart_tx_dma.o
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chip-$(CONFIG_STREAM_USB)+=usb-stream.o
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chip-$(CONFIG_WATCHDOG)+=watchdog.o
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chip-$(HAS_TASK_CONSOLE)+=uart.o
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chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
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chip-$(HAS_TASK_POWERLED)+=power_led.o
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chip-$(CONFIG_FLASH)+=flash-$(CHIP_FAMILY).o
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ifdef CONFIG_FLASH
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chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o
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chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o
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endif
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chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
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chip-$(CONFIG_PWM)+=pwm.o
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chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o
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chip-$(CONFIG_USB_CONSOLE)+=usb_console.o
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chip-$(CONFIG_USB_GPIO)+=usb_gpio.o
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chip-$(CONFIG_USB_HID)+=usb_hid.o
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chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
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chip-$(CONFIG_USB_SPI)+=usb_spi.o
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