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dd9e4fa427
Ensure that a new chip doesn't default to one of the possible alternate function selection schemes, requiring it to pick one or implement something new. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I3650fa0c99bbf541039a778f4d6398f0a549f1b2 Reviewed-on: https://chromium-review.googlesource.com/282601 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
153 lines
3.4 KiB
C
153 lines
3.4 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* PWM control module for STM32 */
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#include "clock.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "pwm.h"
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#include "pwm_chip.h"
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#include "registers.h"
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#include "util.h"
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static int using_pwm[PWM_CH_COUNT];
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void pwm_set_duty(enum pwm_channel ch, int percent)
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{
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const struct pwm_t *pwm = pwm_channels + ch;
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timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
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ASSERT((percent >= 0) && (percent <= 100));
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tim->ccr[pwm->channel] = percent;
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}
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int pwm_get_duty(enum pwm_channel ch)
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{
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const struct pwm_t *pwm = pwm_channels + ch;
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timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
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return tim->ccr[pwm->channel];
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}
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static void pwm_configure(enum pwm_channel ch)
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{
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const struct pwm_t *pwm = pwm_channels + ch;
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const struct gpio_info *gpio = gpio_list + pwm->pin;
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timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
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volatile unsigned *ccmr = NULL;
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if (using_pwm[ch])
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return;
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#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
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gpio_set_alternate_function(gpio->port, gpio->mask, pwm->gpio_alt_func);
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#elif defined(CHIP_FAMILY_STM32L)
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gpio_set_alternate_function(gpio->port, gpio->mask,
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GPIO_ALT_TIM(pwm->tim.id));
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#else
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#error "GPIO alternate function selection not implemented for chip family."
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#endif
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/* Enable timer */
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__hw_timer_enable_clock(pwm->tim.id, 1);
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/* Disable counter during setup */
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tim->cr1 = 0x0000;
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/*
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* CPU clock / PSC determines how fast the counter operates.
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* ARR determines the wave period, CCRn determines duty cycle.
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* Thus, frequency = cpu_freq / PSC / ARR. so:
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*
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* frequency = cpu_freq / (cpu_freq/10000 + 1) / (99 + 1) = 100 Hz.
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*/
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tim->psc = clock_get_freq() / 10000 - 1;
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tim->arr = 99;
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if (pwm->channel <= 2) /* Channel ID starts from 1 */
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ccmr = &tim->ccmr1;
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else
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ccmr = &tim->ccmr2;
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/* Output, PWM mode 1, preload enable */
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if (pwm->channel & 0x1)
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*ccmr = (6 << 4) | (1 << 3);
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else
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*ccmr = (6 << 12) | (1 << 11);
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/* Output enable. Set active high/low. */
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if (pwm->flags & PWM_CONFIG_ACTIVE_LOW)
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tim->ccer = 3 << (pwm->channel * 4 - 4);
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else
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tim->ccer = 1 << (pwm->channel * 4 - 4);
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/*
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* Main output enable.
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* TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't
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* harmful on STM32L.
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*/
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tim->bdtr |= (1 << 15);
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/* Generate update event to force loading of shadow registers */
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tim->egr |= 1;
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/* Enable auto-reload preload, start counting */
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tim->cr1 |= (1 << 7) | (1 << 0);
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using_pwm[ch] = 1;
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}
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static void pwm_disable(enum pwm_channel ch)
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{
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const struct pwm_t *pwm = pwm_channels + ch;
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timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base);
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if (using_pwm[ch] == 0)
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return;
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/* Main output disable */
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tim->bdtr &= ~(1 << 15);
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/* Disable counter */
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tim->cr1 &= ~0x1;
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/* Disable timer clock */
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__hw_timer_enable_clock(pwm->tim.id, 0);
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using_pwm[ch] = 0;
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}
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void pwm_enable(enum pwm_channel ch, int enabled)
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{
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if (enabled)
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pwm_configure(ch);
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else
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pwm_disable(ch);
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}
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int pwm_get_enabled(enum pwm_channel ch)
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{
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return using_pwm[ch];
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}
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static void pwm_reconfigure(enum pwm_channel ch)
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{
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using_pwm[ch] = 0;
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pwm_configure(ch);
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}
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/**
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* Handle clock frequency change
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*/
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static void pwm_freq_change(void)
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{
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int i;
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for (i = 0; i < PWM_CH_COUNT; ++i)
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if (using_pwm[i])
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pwm_reconfigure(i);
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, pwm_freq_change, HOOK_PRIO_DEFAULT);
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