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911de4d175
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
58 lines
1.2 KiB
C
58 lines
1.2 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Atomic operations for Andes */
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#ifndef __CROS_EC_ATOMIC_H
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#define __CROS_EC_ATOMIC_H
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#include "common.h"
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#include "cpu.h"
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#include "task.h"
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static inline void atomic_clear(uint32_t volatile *addr, uint32_t bits)
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{
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uint32_t int_mask = get_int_mask();
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interrupt_disable();
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*addr &= ~bits;
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set_int_mask(int_mask);
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}
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static inline void atomic_or(uint32_t volatile *addr, uint32_t bits)
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{
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uint32_t int_mask = get_int_mask();
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interrupt_disable();
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*addr |= bits;
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set_int_mask(int_mask);
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}
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static inline void atomic_add(uint32_t volatile *addr, uint32_t value)
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{
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uint32_t int_mask = get_int_mask();
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interrupt_disable();
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*addr += value;
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set_int_mask(int_mask);
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}
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static inline void atomic_sub(uint32_t volatile *addr, uint32_t value)
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{
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uint32_t int_mask = get_int_mask();
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interrupt_disable();
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*addr -= value;
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set_int_mask(int_mask);
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}
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static inline uint32_t atomic_read_clear(uint32_t volatile *addr)
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{
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uint32_t val;
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uint32_t int_mask = get_int_mask();
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interrupt_disable();
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val = *addr;
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*addr = 0;
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set_int_mask(int_mask);
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return val;
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}
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#endif /* __CROS_EC_ATOMIC_H */
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