mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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14bd917343
Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
116 lines
2.7 KiB
Tcl
116 lines
2.7 KiB
Tcl
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Command automation for NPCX5M5G chip
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# Program spi flash
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source [find mem_helper.tcl]
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proc flash_npcx {image_path image_offset image_size spifw_image} {
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set UPLOAD_FLAG 0x200C4000;
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echo "*** NPCX Reset and halt CPU first ***"
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reset halt
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# Clear whole 96KB Code RAM
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mwb 0x100A8000 0xFF 0x18000
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# Upload binary image to Code RAM
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load_image $image_path 0x100A8000
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# Upload program spi image FW to lower 16KB Data RAM
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load_image $spifw_image 0x200C0000
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# Set sp to upper 16KB Data RAM
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reg sp 0x200C8000
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# Set spi offset address of uploaded image
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reg r0 $image_offset
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# Set spi program size of uploaded image
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reg r1 $image_size
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# Set pc to start of spi program function
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reg pc 0x200C0001
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# Clear upload flag
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mww $UPLOAD_FLAG 0x0
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echo "*** Program ... ***"
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# Start to program spi flash
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resume
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# Wait for any pending flash operations to complete
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while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1000 }
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if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} {
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echo "*** Program Fail ***"
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} else {
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echo "*** Program Done ***"
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}
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# Halt CPU
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halt
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}
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proc flash_npcx_ro {image_dir image_offset} {
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set MPU_RNR 0xE000ED98;
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set MPU_RASR 0xE000EDA0;
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# 96 KB for RO& RW regions
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set fw_size 0x18000
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# images path
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set ro_image_path $image_dir/ec.RO.flat
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set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin
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# Halt CPU first
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halt
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# diable MPU for Data RAM
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mww $MPU_RNR 0x1
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mww $MPU_RASR 0x0
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echo "*** Start to program RO region ***"
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# Write to lower 96kB from offset
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flash_npcx $ro_image_path $image_offset $fw_size $spifw_image
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echo "*** Finish program RO region ***"
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}
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proc flash_npcx_all {image_dir image_offset} {
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set MPU_RNR 0xE000ED98;
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set MPU_RASR 0xE000EDA0;
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# 96 KB for RO& RW regions
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set fw_size 0x18000
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# 8M spi-flash
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set flash_size 0x800000
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# images path
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set ro_image_path $image_dir/RO/ec.RO.flat
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set rw_image_path $image_dir/RW/ec.RW.bin
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set spifw_image $image_dir/chip/npcx/spiflashfw/ec_npcxflash.bin
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# images offset
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set rw_image_offset [expr ($image_offset + 0x20000)]
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# Halt CPU first
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halt
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# diable MPU for Data RAM
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mww $MPU_RNR 0x1
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mww $MPU_RASR 0x0
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echo "*** Start to program RO region ***"
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# Write to lower 96kB from offset
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flash_npcx $ro_image_path $image_offset $fw_size $spifw_image
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echo "*** Finish program RO region ***\r\n"
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echo "*** Start to program RW region ***"
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# Write to upper 96kB from offset
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flash_npcx $rw_image_path $rw_image_offset $fw_size $spifw_image
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echo "*** Finish program RW region ***\r\n"
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}
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proc reset_halt_cpu { } {
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echo "*** NPCX Reset and halt CPU first ***"
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reset halt
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}
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