Aaron Durbin bc07f5d935 x86: add rom cache variable MTRR index to tables ...

Downstream payloads may need to take advantage of caching the
ROM for performance reasons. Add the ability to communicate the
variable range MTRR index to use to perform the caching enablement.

An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the coreboot tables. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.

Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2013-03-29 20:09:36 +01:00

..

coreboot_tables.h

x86: add rom cache variable MTRR index to tables

2013-03-29 20:09:36 +01:00

elf_boot.h

Since some people disapprove of white space cleanups mixed in regular commits

2010-04-27 06:56:47 +00:00

elf.h

Allow dynamic size for the {s,}elfboot bounce buffer.

2009-05-13 16:27:25 +00:00

tables.h

Unify coreboot table generation

2013-03-22 00:17:55 +01:00