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90215a4494
CONFIG_FMAP is now defined by default, because all platforms other than the host unit tests use it. No functional changes, just renaming config options and removing dead code. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: Ie6496310c822491068e2fa6976933486f26badb0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63271 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Chip config header file */
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* Memory mapping */
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#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
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#define CONFIG_FLASH_BASE ((uintptr_t)__host_flash)
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#define CONFIG_FLASH_BANK_SIZE 0x1000
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#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
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#define CONFIG_RAM_BASE 0x0 /* Not supported */
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#define CONFIG_RAM_SIZE 0x0 /* Not supported */
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/* Size of one firmware image in flash */
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#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
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#define CONFIG_FW_RO_OFF 0
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#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
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#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
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#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
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/*
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* Put this after RO to give RW more space and make RO write protect region
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* contiguous.
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*/
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#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
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#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
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/* Maximum number of deferrable functions */
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#define DEFERRABLE_MAX_COUNT 8
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL (250 * MSEC)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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