Paul Menzel be8d23a3b5 cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable Start_vid ...

When adding support for PSS object generation for AMD pre Family Fh CPUs
(199c694f) the function `pstates_algorithm` was copied and adapted, but
`Start_vid` is not needed anymore as a static table is used. I’d remove
the variable, but Ron Minnich requested to leave it there for
documentation purposes. So just comment it out.

Change-Id: I3002951d168cade6461941c16d78373c47792e13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4036
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

2014-01-15 22:20:20 +01:00

..

arch

lib: Make log2() available in romstage on ARM, not just x86

2014-01-13 04:03:06 +01:00

console

Remove sprintf

2014-01-10 18:08:31 +01:00

cpu

cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable Start_vid

2014-01-15 22:20:20 +01:00

device

lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content

2014-01-12 17:41:02 +01:00

drivers

xpowers/axp209: Add helper to set voltages from devicetree config

2014-01-13 06:24:54 +01:00

ec

acpi/ec: Add missing delays

2014-01-12 18:06:06 +01:00

include

Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

2014-01-15 15:26:48 +01:00

lib

lib: Add log2 ceiling function

2014-01-14 14:14:46 +01:00

mainboard

ROMSIZE: Add option for 12M chips.

2014-01-15 16:35:53 +01:00

northbridge

Intel (sandy/ivy): Avoid calling cbmem_initialize() twice

2014-01-15 15:33:54 +01:00

southbridge

ibexpeak / bd82x6x: Make SATA mode user-visible option.

2014-01-12 18:03:23 +01:00

superio

superio: Uncomment the w83627uhg UART clock source initialization

2014-01-03 18:47:22 +01:00

vendorcode

CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file

2014-01-12 17:41:58 +01:00

Kconfig

Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

2014-01-15 15:26:48 +01:00