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https://github.com/Telecominfraproject/OpenCellular.git
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59c03bc4c6
cr50 has three UARTs that it will be using. This change modifies the uart api to specify which uart to use. BUG=chrome-os-partner:50702 BRANCH=none TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the different UARTs can be used. Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333402 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "clock.h"
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#include "common.h"
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#include "gpio.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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struct uartn_interrupts {
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int tx_int;
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int rx_int;
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};
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static struct uartn_interrupts interrupt[] = {
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{GC_IRQNUM_UART0_TXINT, GC_IRQNUM_UART0_RXINT},
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{GC_IRQNUM_UART1_TXINT, GC_IRQNUM_UART1_RXINT},
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{GC_IRQNUM_UART2_TXINT, GC_IRQNUM_UART2_RXINT},
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};
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void uartn_tx_start(int uart)
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{
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if (!uart_init_done())
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return;
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/* If interrupt is already enabled, nothing to do */
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if (GR_UART_ICTRL(uart) & GC_UART_ICTRL_TX_MASK)
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return;
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/* Do not allow deep sleep while transmit in progress */
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disable_sleep(SLEEP_MASK_UART);
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/*
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* Re-enable the transmit interrupt, then forcibly trigger the
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* interrupt. This works around a hardware problem with the
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* UART where the FIFO only triggers the interrupt when its
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* threshold is _crossed_, not just met.
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*/
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/* TODO(crosbug.com/p/33819): Do we need this hack here? Find out. */
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REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
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GC_UART_ICTRL_TX_LSB, 1);
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task_trigger_irq(interrupt[uart].tx_int);
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}
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void uartn_tx_stop(int uart)
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{
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/* Disable the TX interrupt */
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REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
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GC_UART_ICTRL_TX_LSB, 0);
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/* Re-allow deep sleep */
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enable_sleep(SLEEP_MASK_UART);
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}
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int uartn_tx_in_progress(int uart)
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{
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/* Transmit is in progress unless the TX FIFO is empty and idle. */
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return !(GR_UART_STATE(uart) & (GC_UART_STATE_TXIDLE_MASK |
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GC_UART_STATE_TXEMPTY_MASK));
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}
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void uartn_tx_flush(int uart)
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{
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/* Wait until TX FIFO is idle. */
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while (uartn_tx_in_progress(uart))
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;
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}
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int uartn_tx_ready(int uart)
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{
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/* True if the TX buffer is not completely full */
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return !(GR_UART_STATE(uart) & GC_UART_STATE_TX_MASK);
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}
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int uartn_rx_available(int uart)
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{
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/* True if the RX buffer is not completely empty. */
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return !(GR_UART_STATE(uart) & GC_UART_STATE_RXEMPTY_MASK);
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}
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void uartn_write_char(int uart, char c)
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{
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/* Wait for space in transmit FIFO. */
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while (!uartn_tx_ready(uart))
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;
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GR_UART_WDATA(uart) = c;
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}
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int uartn_read_char(int uart)
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{
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return GR_UART_RDATA(uart);
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}
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void uartn_disable_interrupt(int uart)
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{
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task_disable_irq(interrupt[uart].tx_int);
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task_disable_irq(interrupt[uart].rx_int);
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}
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void uartn_enable_interrupt(int uart)
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{
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task_enable_irq(interrupt[uart].tx_int);
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task_enable_irq(interrupt[uart].rx_int);
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}
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void uartn_init(int uart)
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{
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long long setting = (16 * (1 << UART_NCO_WIDTH) *
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(long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ);
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/* set frequency */
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GR_UART_NCO(uart) = setting;
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/*
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* Interrupt when RX fifo has anything, when TX fifo <= half
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* empty and reset (clear) both FIFOs
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*/
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GR_UART_FIFO(uart) = 0x63;
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/*
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* TX enable, RX enable, HW flow control disabled, no
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* loopback
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*/
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GR_UART_CTRL(uart) = 0x03;
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/* enable RX interrupts in block */
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/* Note: doesn't do anything unless turned on in NVIC */
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GR_UART_ICTRL(uart) = 0x02;
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}
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