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b6991dd96d
Support protection of regions that aren't aligned to a power of 2 by using two MPU entries, and taking advantage of the sub-region feature. Also protect code RAM from being overwritten, on parts that use external storage. BUG=chromium:782244 BRANCH=None TEST=On kevin, call: mpu_protect_data_ram(); mpu_protect_code_ram(); mpu_enable(); Verify that first call results in the following update_region params: addr: 0x200c2000 size: 0xc01d Decoded: Protect 24K region Verify that second call results in the following params: addr: 0x100a8000 size: 0xc021 Decoded: Protect 96K region addr: 0x100c0000 size: 0xf01b Decoded: Protect remaining 8K region Also verify that writes to beginning and end of code ram region trigger data access violation after enabling protection. Also verify that sysjump fails. Change-Id: Ieb7a4ec3a089e8a2d29f231e1e3acf2e78e560a1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/757721 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* MPU module for Cortex-M3 */
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#ifndef __CROS_EC_MPU_H
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#define __CROS_EC_MPU_H
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#include "common.h"
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/*
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* Region assignment. 7 as the highest, a higher index has a higher priority.
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* For example, using 7 for .iram.text allows us to mark entire RAM XN except
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* .iram.text, which is used for hibernation.
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* Region assignment is currently wasteful and can be changed if more
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* regions are needed in the future. For example, a second region may not
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* be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be
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* made mutually exclusive.
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*/
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enum mpu_region {
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REGION_DATA_RAM = 0, /* For internal data RAM */
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REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
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REGION_CODE_RAM = 2, /* For internal code RAM */
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REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
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REGION_STORAGE = 4, /* For mapped internal storage */
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REGION_STORAGE2 = 5, /* Second region for unaligned size */
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REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
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REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
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};
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#define MPU_TYPE REG32(0xe000ed90)
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#define MPU_CTRL REG32(0xe000ed94)
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#define MPU_NUMBER REG32(0xe000ed98)
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#define MPU_BASE REG32(0xe000ed9c)
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#define MPU_SIZE REG16(0xe000eda0)
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#define MPU_ATTR REG16(0xe000eda2)
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#define MPU_CTRL_PRIVDEFEN (1 << 2)
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#define MPU_CTRL_HFNMIENA (1 << 1)
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#define MPU_CTRL_ENABLE (1 << 0)
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/*
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* XN (execute never) bit. It's bit 12 if accessed by halfword.
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* 0: XN off
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* 1: XN on
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*/
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#define MPU_ATTR_XN (1 << 12)
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/* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
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#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
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#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
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#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
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/* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
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* datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
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#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
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#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
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/**
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* Enable MPU
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*/
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void mpu_enable(void);
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/**
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* Returns the value of MPU type register
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*
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* Bit fields:
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* [15:8] Number of the data regions implemented or 0 if MPU is not present.
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* [1] 0: unified (no distinction between instruction and data)
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* 1: separated
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*/
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uint32_t mpu_get_type(void);
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/* Location of iram.text */
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extern char __iram_text_start;
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extern char __iram_text_end;
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/**
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* Protect RAM from code execution
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*/
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int mpu_protect_data_ram(void);
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/**
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* Protect code RAM from being overwritten
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*/
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int mpu_protect_code_ram(void);
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/**
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* Protect internal mapped flash memory from code execution
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*/
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int mpu_lock_ro_flash(void);
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int mpu_lock_rw_flash(void);
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/**
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* Initialize MPU.
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* It disables all regions if MPU is implemented. Otherwise, returns
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* EC_ERROR_UNIMPLEMENTED.
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*/
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int mpu_pre_init(void);
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#endif /* __CROS_EC_MPU_H */
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