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6ec72c9b4f
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <console/uart.h>
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#if CONFIG_USE_OPTION_TABLE
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#include <option.h>
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#include "option_table.h"
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#endif
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unsigned int default_baudrate(void)
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{
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#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE
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static const unsigned baud[8] =
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{ 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 };
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unsigned b_index = 0;
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#if defined(__PRE_RAM__)
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b_index = read_option(baud_rate, 0xff);
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#else
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if (get_option(&b_index, "baud_rate") != CB_SUCCESS)
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b_index = 0xff;
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#endif
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if (b_index < 8)
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return baud[b_index];
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#endif
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return CONFIG_TTYS0_BAUD;
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}
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/* Calculate divisor. Do not floor but round to nearest integer. */
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unsigned int uart_baudrate_divisor(unsigned int baudrate,
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unsigned int refclk, unsigned int oversample)
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{
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return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
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}
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#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER)
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unsigned int uart_input_clock_divider(void)
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{
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/* Specify the default oversample rate for the UART.
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*
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* UARTs oversample the receive data. The UART's input clock first
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* enters the baud-rate divider to generate the oversample clock. Then
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* the UART typically divides the result by 16. The asynchronous
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* receive data is synchronized with the oversample clock and when a
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* start bit is detected the UART delays half a bit time using the
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* oversample clock. Samples are then taken to verify the start bit and
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* if present, samples are taken for the rest of the frame.
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*/
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return 16;
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}
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#endif
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#if !IS_ENABLED(CONFIG_UART_OVERRIDE_REFCLK)
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unsigned int uart_platform_refclk(void)
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{
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/* Specify the default input clock frequency for the UART.
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*
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* The older UART's used an input clock frequency of 1.8432 MHz which
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* with the 16x oversampling provided the maximum baud-rate of 115200.
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* Specify this as maximum baud-rate multiplied by oversample so that
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* it is obvious that the maximum baud rate is 115200 when divided by
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* oversample clock. Also note that crystal on the board does not
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* change when software selects another input clock divider.
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*/
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return 115200 * 16;
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}
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#endif
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