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https://github.com/Telecominfraproject/OpenCellular.git
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59dccac4da
SERIRQ bug: PMC1/2 share the same IRQ number 1 with default setting. Enable it will influence 8042 protocols since KBC has no data but IRQ 1 is issued by PMC. AC detection bug: GPIO definitions between AC_PRESENT and ACOK mismatched. AC_PRESENT will always be high even we don't plug the adaptor. Modified drivers: 1. lpc.c: Remove enabling SERIRQ for PMC1/2 and disable IRQ12 for Mouse. 2. config_flash_layout.h: Modified for adjusting RAM size. 3. gpio.inc: Modified GPIO definitions for AC issue 4. board.h: Modified for adjusting RAM size and add support for ACC 5. board.c: Add support for ACC and adjust ADC max value BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ib330ef4078e4b06f1c01a2a6316e468b43d7a8d9 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/311933 Reviewed-by: Randall Spangler <rspangler@chromium.org>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
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#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
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/*
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* npcx flash layout:
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* - Memory-mapped external SPI.
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* - Image header at the beginning of protected region, followed by RO image.
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* - RW image starts at the second half of flash.
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*/
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/* Memmapped, external SPI */
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#define CONFIG_EXTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Storage is memory-mapped, but program runs from SRAM */
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#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
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#undef CONFIG_FLASH_PSTATE
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
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/* Header support which is used by booter to copy FW from flash to code ram */
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#define NPCX_RO_HEADER
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#define CONFIG_RO_HDR_MEM_OFF 0x0
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#define CONFIG_RO_HDR_SIZE 0x40
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/* RO firmware offset in flash */
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_SIZE (96 * 1024) /* 96KB for RO FW */
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/* RW firmware offset in flash */
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#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF
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#define CONFIG_RW_SIZE CONFIG_RO_SIZE /* 96KB for RW FW */
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/* The storage offset of ec.R*.flat which is used for firmware_image.lds */
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#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
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#define CONFIG_RW_STORAGE_OFF 0
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#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
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