Kyösti Mälkki cb08e169cf CBMEM intel: Define get_top_of_ram() once per chipset ...

Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

2014-01-15 15:29:52 +01:00

..

arch

lib: Make log2() available in romstage on ARM, not just x86

2014-01-13 04:03:06 +01:00

console

Remove sprintf

2014-01-10 18:08:31 +01:00

cpu

nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash

2014-01-15 15:27:33 +01:00

device

lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content

2014-01-12 17:41:02 +01:00

drivers

xpowers/axp209: Add helper to set voltages from devicetree config

2014-01-13 06:24:54 +01:00

ec

acpi/ec: Add missing delays

2014-01-12 18:06:06 +01:00

include

Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

2014-01-15 15:26:48 +01:00

lib

lib: Add log2 ceiling function

2014-01-14 14:14:46 +01:00

mainboard

Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

2014-01-15 15:26:48 +01:00

northbridge

CBMEM intel: Define get_top_of_ram() once per chipset

2014-01-15 15:29:52 +01:00

southbridge

ibexpeak / bd82x6x: Make SATA mode user-visible option.

2014-01-12 18:03:23 +01:00

superio

superio: Uncomment the w83627uhg UART clock source initialization

2014-01-03 18:47:22 +01:00

vendorcode

CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file

2014-01-12 17:41:58 +01:00

Kconfig

Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

2014-01-15 15:26:48 +01:00