Kevin Chiu a0f6f9bdbc google/pyro: Set PL2 override to 15000mW ...

This patch sets PL2 override value to 15W in RAPL registers
and sets DPTF PL2 Max to 15W

BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17779
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-12-12 17:51:36 +01:00

..

acpi

src/acpi: Capitalize ACPI and SATA

2016-07-31 19:25:40 +02:00

arch

ACPI S3: Hide acpi_slp_type

2016-12-11 09:00:40 +01:00

commonlib

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

console

Hook up libhwbase in ramstage

2016-11-29 23:45:40 +01:00

cpu

ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default

2016-12-11 09:12:48 +01:00

device

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

drivers

drivers/intel/fsp2_0: Include stddef.h in soc_binding.h

2016-12-11 20:03:43 +01:00

ec

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

include

x86 SMM: Fix use with RELOCATABLE_RAMSTAGE

2016-12-11 08:56:40 +01:00

lib

cbfs: Add API to locate a file from specific region

2016-12-10 03:16:55 +01:00

mainboard

google/pyro: Set PL2 override to 15000mW

2016-12-12 17:51:36 +01:00

northbridge

nb/intel/i945: Make pci_mmio_size a devicetree parameter

2016-12-11 14:17:06 +01:00

soc

x86 SMM: Fix use with RELOCATABLE_RAMSTAGE

2016-12-11 08:56:40 +01:00

southbridge

intel/i945: Use romstage_handoff for S3

2016-12-11 08:58:07 +01:00

superio

sio/ite/it8783ef: New super i/o chip

2016-12-07 20:02:17 +01:00

vboot

commonlib/include: remove NEED_VB20_INTERNALS

2016-11-19 16:57:27 +01:00

vendorcode

buildsystem: Drop explicit (k)config.h includes

2016-12-08 19:46:53 +01:00

Kconfig

ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default

2016-12-11 09:12:48 +01:00