mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-10 09:31:51 +00:00
d5ade1b2ed
And change some direct uart_printf()/uart_puts() output to console output methods instead. Disable unused comxtest debug command. No other functional changes. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; should still see debug output with reset flags Change-Id: I57fe6bb781a1ba7884afa6d090b74a92f45a53cc Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36835
150 lines
3.1 KiB
C
150 lines
3.1 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USART driver for Chrome EC */
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#include <stdarg.h>
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#include "board.h"
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#include "config.h"
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#include "clock.h"
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#include "registers.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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/* Baud rate for UARTs */
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#define BAUD_RATE 115200
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/* Console USART index */
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#define UARTN CONFIG_CONSOLE_UART
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static int init_done; /* Initialization done? */
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static int should_stop; /* Last TX control action */
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int uart_init_done(void)
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{
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return init_done;
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}
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void uart_tx_start(void)
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{
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disable_sleep(SLEEP_MASK_UART);
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STM32_USART_CR1(UARTN) |= 0x80;
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should_stop = 0;
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task_trigger_irq(STM32_IRQ_USART(UARTN));
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}
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void uart_tx_stop(void)
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{
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STM32_USART_CR1(UARTN) &= ~0x80;
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should_stop = 1;
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enable_sleep(SLEEP_MASK_UART);
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}
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int uart_tx_stopped(void)
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{
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return !(STM32_USART_CR1(UARTN) & 0x80);
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}
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void uart_tx_flush(void)
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{
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while (!(STM32_USART_SR(UARTN) & 0x80))
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;
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}
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int uart_tx_ready(void)
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{
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return STM32_USART_SR(UARTN) & 0x80;
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}
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int uart_rx_available(void)
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{
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return STM32_USART_SR(UARTN) & 0x20;
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}
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void uart_write_char(char c)
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{
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/* we normally never wait here since uart_write_char is normally called
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* when the buffer is ready, excepted when we insert a carriage return
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* before a line feed in the interrupt routine.
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*/
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while (!uart_tx_ready()) ;
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STM32_USART_DR(UARTN) = c;
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}
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int uart_read_char(void)
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{
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return STM32_USART_DR(UARTN);
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}
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void uart_disable_interrupt(void)
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{
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task_disable_irq(STM32_IRQ_USART(UARTN));
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}
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void uart_enable_interrupt(void)
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{
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task_enable_irq(STM32_IRQ_USART(UARTN));
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}
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/* Interrupt handler for console USART */
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static void uart_interrupt(void)
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{
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/*
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* Disable the TX empty interrupt before filling the TX buffer since it
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* needs an actual write to DR to be cleared.
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*/
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STM32_USART_CR1(UARTN) &= ~0x80;
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/* Read input FIFO until empty, then fill output FIFO */
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uart_process();
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/*
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* Re-enable TX empty interrupt only if it was not disabled by
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* uart_process.
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*/
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if (!should_stop)
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STM32_USART_CR1(UARTN) |= 0x80;
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}
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DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2);
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void uart_init(void)
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{
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/* Enable USART clock */
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if (UARTN == 1)
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STM32_RCC_APB2ENR |= 1 << 14; /* USART1 */
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else if (UARTN == 2)
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STM32_RCC_APB1ENR |= 1 << 17; /* USART2 */
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else if (UARTN == 3)
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STM32_RCC_APB1ENR |= 1 << 18; /* USART3 */
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else if (UARTN == 4)
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STM32_RCC_APB1ENR |= 1 << 19; /* USART4 */
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else if (UARTN == 5)
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STM32_RCC_APB1ENR |= 1 << 20; /* USART5 */
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/* UART enabled, 8 Data bits, oversampling x16, no parity,
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* RXNE interrupt, TX and RX enabled.
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*/
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STM32_USART_CR1(UARTN) = 0x202C;
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/* 1 stop bit, no fancy stuff */
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STM32_USART_CR2(UARTN) = 0x0000;
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/* DMA disabled, special modes disabled, error interrupt disabled */
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STM32_USART_CR3(UARTN) = 0x0000;
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/* Select the baud rate
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* using x16 oversampling (OVER8 == 0)
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*/
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STM32_USART_BRR(UARTN) = DIV_ROUND_NEAREST(CPU_CLOCK, BAUD_RATE);
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/* Enable interrupts */
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task_enable_irq(STM32_IRQ_USART(UARTN));
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init_done = 1;
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}
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