mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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a04fc68e72
This combines stm32 and chip/g usb_i2c interfaces so they will not diverge. Note that this fixes the chip/g implementation to use 8-bit i2c addresses. BUG=chrome-os-partner:57059 BRANCH=none TEST=servod interacts with servo_micro and servo_v4 Change-Id: Ibff217d84b132556202c8a71e3d42c07d546c634 Reviewed-on: https://chromium-review.googlesource.com/405108 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
154 lines
5.1 KiB
C
154 lines
5.1 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "consumer.h"
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#include "producer.h"
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#include "registers.h"
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#include "task.h"
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#include "usb_descriptor.h"
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#include "util.h"
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#ifndef __CROS_USB_I2C_H
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#define __CROS_USB_I2C_H
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/*
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* Command:
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* +----------+-----------+---------------+---------------+---------------+
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* | port: 1B | addr: 1B | wr count : 1B | rd count : 1B | data : <= 60B |
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* +----------+-----------+---------------+---------------+---------------+
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*
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* port address: 1 byte, i2c interface index
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*
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* slave address: 1 byte, i2c 7-bit bus address
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*
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* write count: 1 byte, zero based count of bytes to write
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*
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* read count: 1 byte, zero based count of bytes to read
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*
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* data: write payload up to 60 bytes of data to write,
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* length must match write count
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*
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* Response:
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* +-------------+---+---+-----------------------+
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* | status : 2B | 0 | 0 | read payload : <= 60B |
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* +-------------+---+---+-----------------------+
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*
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* status: 2 byte status
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* 0x0000: Success
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* 0x0001: I2C timeout
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* 0x0002: Busy, try again
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* This can happen if someone else has acquired the shared memory
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* buffer that the I2C driver uses as /dev/null
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* 0x0003: Write count invalid (> 60 bytes, or mismatch with payload)
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* 0x0004: Read count invalid (> 60 bytes)
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* 0x0005: The port specified is invalid.
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* 0x8000: Unknown error mask
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* The bottom 15 bits will contain the bottom 15 bits from the EC
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* error code.
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*
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* read payload: up to 60 bytes of data read from I2C, length will match
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* requested read count
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*/
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enum usb_i2c_error {
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USB_I2C_SUCCESS = 0x0000,
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USB_I2C_TIMEOUT = 0x0001,
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USB_I2C_BUSY = 0x0002,
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USB_I2C_WRITE_COUNT_INVALID = 0x0003,
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USB_I2C_READ_COUNT_INVALID = 0x0004,
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USB_I2C_PORT_INVALID = 0x0005,
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USB_I2C_UNKNOWN_ERROR = 0x8000,
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};
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#define USB_I2C_MAX_WRITE_COUNT 60
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#define USB_I2C_MAX_READ_COUNT 60
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BUILD_ASSERT(USB_MAX_PACKET_SIZE == (1 + 1 + 1 + 1 + USB_I2C_MAX_WRITE_COUNT));
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BUILD_ASSERT(USB_MAX_PACKET_SIZE == (2 + 1 + 1 + USB_I2C_MAX_READ_COUNT));
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/*
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* Compile time Per-USB gpio configuration stored in flash. Instances of this
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* structure are provided by the user of the USB i2c. This structure binds
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* together all information required to operate a USB i2c.
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*/
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struct usb_i2c_config {
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uint16_t *buffer;
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/* Deferred function to call to handle SPI request. */
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const struct deferred_data *deferred;
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struct consumer const consumer;
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struct queue const *tx_queue;
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};
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extern struct consumer_ops const usb_i2c_consumer_ops;
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/*
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* Convenience macro for defining a USB I2C bridge driver.
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*
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* NAME is used to construct the names of the trampoline functions and the
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* usb_i2c_config struct, the latter is just called NAME.
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*
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* INTERFACE is the index of the USB interface to associate with this
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* I2C driver.
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*
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* INTERFACE_NAME is the index of the USB string descriptor (iInterface).
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*
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* ENDPOINT is the index of the USB bulk endpoint used for receiving and
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* transmitting bytes.
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*/
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#define USB_I2C_CONFIG(NAME, \
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INTERFACE, \
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INTERFACE_NAME, \
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ENDPOINT) \
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static uint16_t \
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CONCAT2(NAME, _buffer_)[USB_MAX_PACKET_SIZE/2]; \
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static void CONCAT2(NAME, _deferred_)(void); \
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DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \
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static struct queue const CONCAT2(NAME, _to_usb_); \
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static struct queue const CONCAT3(usb_to_, NAME, _); \
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USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), \
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INTERFACE, \
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USB_CLASS_VENDOR_SPEC, \
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USB_SUBCLASS_GOOGLE_I2C, \
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USB_PROTOCOL_GOOGLE_I2C, \
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INTERFACE_NAME, \
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ENDPOINT, \
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USB_MAX_PACKET_SIZE, \
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USB_MAX_PACKET_SIZE, \
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CONCAT3(usb_to_, NAME, _), \
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CONCAT2(NAME, _to_usb_)) \
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struct usb_i2c_config const NAME = { \
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.buffer = CONCAT2(NAME, _buffer_), \
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.deferred = &CONCAT2(NAME, _deferred__data), \
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.consumer = { \
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.queue = &CONCAT3(usb_to_, NAME, _), \
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.ops = &usb_i2c_consumer_ops, \
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}, \
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.tx_queue = &CONCAT2(NAME, _to_usb_), \
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}; \
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static struct queue const CONCAT2(NAME, _to_usb_) = \
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QUEUE_DIRECT(USB_MAX_PACKET_SIZE, uint8_t, \
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null_producer, CONCAT2(NAME, _usb_).consumer); \
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static struct queue const CONCAT3(usb_to_, NAME, _) = \
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QUEUE_DIRECT(USB_MAX_PACKET_SIZE, uint8_t, \
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CONCAT2(NAME, _usb_).producer, NAME.consumer); \
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static void CONCAT2(NAME, _deferred_)(void) \
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{ usb_i2c_deferred(&NAME); }
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/*
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* Handle I2C request in a deferred callback.
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*/
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void usb_i2c_deferred(struct usb_i2c_config const *config);
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/*
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* These functions should be implemented by the board to provide any board
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* specific operations required to enable or disable access to the I2C device.
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*/
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int usb_i2c_board_enable(void);
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void usb_i2c_board_disable(int debounce);
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#endif /* __CROS_USB_I2C_H */
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