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d5cb026142
These likely indicate errors, so we shold trap them. Possibly this should be reconsidered for production. BUG=chrome-os-partner:10148 TEST=manual: build on all boards build and boot on snow with a special rw command containing a division by 0. See that it is trapped: > rw 0 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :08005eba r2 :00000000 r3 :20001048 r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :0800368a Divide by 0, Forced hard fault, Vector catch mmfs = 02000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 Turn off the cpu_init() setup, and see that it is ignored. > rw 0 read 0x0 = 0x00000000 > Similarly, try an unaligned access with the rw command with this enabled: > rw 1 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000041 r2 :00000001 r3 :200012ac r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :08003686 Unaligned, Forced hard fault, Vector catch mmfs = 01000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 but disabled it works: > rw 1 read 0x1 = 0x5d200010 > Change-Id: Id84f737301e467b3b56a7ac22790e55d672df7d8 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/25410 Reviewed-by: Randall Spangler <rspangler@chromium.org>
50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Cortex-MLM4x processor
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#define CPU_NVIC_CCR CPUREG(0xe000ed14)
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#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
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#define CPU_NVIC_MMFS CPUREG(0xe000ed28)
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#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
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#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
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#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
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#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
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enum {
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CPU_NVIC_MMFS_BFARVALID = 1 << 15,
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CPU_NVIC_MMFS_MFARVALID = 1 << 7,
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CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4,
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CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3,
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CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
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CPU_NVIC_HFSR_FORCED = 1 << 30,
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CPU_NVIC_HFSR_VECTTBL = 1 << 1,
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};
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/* Set up the cpu to detect faults */
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void cpu_init(void);
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#endif /* __CPU_H */
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