mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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34fe8658ab
Remove common code across all PD policy layers to select the requested voltage and build a Request Data Object (RDO). BUG=none BRANCH=samus TEST=Load onto samus and connect zinger. Make sure we request the right voltage (first 5V, then after initial contract is made, 20V). Make sure input current limit is set appropriately by checking limit on EC console using charger command. Change-Id: Ic6bda5e23b2d7b7d710ffdf085e7fbc1b0c3add9 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233673 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
183 lines
5.2 KiB
C
183 lines
5.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USB Power delivery board configuration */
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#ifndef __USB_PD_CONFIG_H
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#define __USB_PD_CONFIG_H
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/* Port and task configuration */
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#define PD_PORT_COUNT 1
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#define PORT_TO_TASK_ID(port) TASK_ID_PD
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#define TASK_ID_TO_PORT(id) 0
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/* Timer selection for baseband PD communication */
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#define TIM_CLOCK_PD_TX_C0 3
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#define TIM_CLOCK_PD_RX_C0 2
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#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
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#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
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/* Timer channel */
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#define TIM_RX_CCR_C0 4
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#define TIM_TX_CCR_C0 4
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/* RX timer capture/compare register */
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#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
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#define TIM_RX_CCR_REG(p) TIM_CCR_C0
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/* TX and RX timer register */
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#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
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#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
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#define TIM_REG_TX(p) TIM_REG_TX_C0
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#define TIM_REG_RX(p) TIM_REG_RX_C0
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/* use the hardware accelerator for CRC */
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#define CONFIG_HW_CRC
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/* TX is using SPI1 on PA6, PB3, and PB5 */
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#define SPI_REGS(p) STM32_SPI1_REGS
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static inline void spi_enable_clock(int port)
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{
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
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}
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#define DMAC_SPI_TX(p) STM32_DMAC_CH3
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/* RX is using COMP1 triggering TIM2 CH4 */
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#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM2_IC4
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#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM2_IC4
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#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
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#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
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#define TIM_CCR_CS 1
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#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
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#define IRQ_COMP STM32_IRQ_COMP
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/* triggers packet detection on comparator falling edge */
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#define EXTI_XTSR STM32_EXTI_FTSR
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#define DMAC_TIM_RX(p) STM32_DMAC_CH7
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/* the pins used for communication need to be hi-speed */
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static inline void pd_set_pins_speed(int port)
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{
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/* 40 MHz pin speed on SPI MISO PA6 */
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STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003000;
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/* 40 MHz pin speed on TIM3_CH4 (PB1) */
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000000C;
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}
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/* Reset SPI peripheral used for TX */
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static inline void pd_tx_spi_reset(int port)
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{
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/* Reset SPI1 */
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STM32_RCC_APB2RSTR |= (1 << 12);
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STM32_RCC_APB2RSTR &= ~(1 << 12);
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}
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/* Drive the CC line from the TX block */
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static inline void pd_tx_enable(int port, int polarity)
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{
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/* put SPI function on TX pin : PA6 is SPI MISO */
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gpio_set_alternate_function(GPIO_A, 0x0040, 5);
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/* set the low level reference */
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gpio_set_level(GPIO_USBC_CC_TX_EN, 1);
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}
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/* Put the TX driver in Hi-Z state */
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static inline void pd_tx_disable(int port, int polarity)
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{
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/* output low on SPI TX (PA6 is SPI1 MISO) to disable the FET */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*6)))
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| (1 << (2*6));
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/* put the low level reference in Hi-Z */
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gpio_set_level(GPIO_USBC_CC_TX_EN, 0);
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}
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/* we know the plug polarity, do the right configuration */
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static inline void pd_select_polarity(int port, int polarity)
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{
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/*
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* use the right comparator : CC1 -> PA1 (COMP1 INP)
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* CC2 -> PA3 (COMP2 INP)
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* use VrefInt / 2 as INM (about 600mV)
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*/
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STM32_COMP_CSR = (STM32_COMP_CSR
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& ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
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| STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
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| STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP2INSEL_VREF12
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| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
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}
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/* Initialize pins used for TX and put them in Hi-Z */
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static inline void pd_tx_init(void)
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{
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gpio_config_module(MODULE_USB_PD, 1);
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}
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static inline void pd_set_host_mode(int port, int enable)
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{
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if (enable) {
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/* We never charging in power source mode */
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gpio_set_level(GPIO_USBC_CHARGE_EN_L, 1);
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/* High-Z is used for host mode. */
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gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 1);
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gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 1);
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} else {
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/* Kill VBUS power supply */
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gpio_set_level(GPIO_USBC_5V_EN, 0);
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/* Pull low for device mode. */
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gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 0);
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gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 0);
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/* Enable the charging path*/
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gpio_set_level(GPIO_USBC_CHARGE_EN_L, 0);
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}
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}
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static inline int pd_adc_read(int port, int cc)
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{
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if (cc == 0)
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return adc_read_channel(ADC_CC1_PD);
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else
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return adc_read_channel(ADC_CC2_PD);
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}
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static inline void pd_set_vconn(int port, int polarity, int enable)
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{
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/* Set VCONN on the opposite CC line from the polarity */
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gpio_set_level(polarity ? GPIO_USBC_VCONN1_EN_L :
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GPIO_USBC_VCONN2_EN_L, !enable);
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}
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static inline int pd_snk_is_vbus_provided(int port)
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{
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return gpio_get_level(GPIO_CHGR_ACOK);
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}
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/* Standard-current DFP : no-connect voltage is 1.55V */
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#define PD_SRC_VNC 1550 /* mV */
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/* UFP-side : threshold for DFP connection detection */
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#define PD_SNK_VA 200 /* mV */
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/* start as a sink in case we have no other power supply/battery */
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#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
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/* delay for the voltage transition on the power supply, chip max is 16us */
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#define PD_POWER_SUPPLY_TRANSITION_DELAY 20000 /* us */
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/* Define typical operating power and max power */
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#define PD_OPERATING_POWER_MW 10000
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#define PD_MAX_POWER_MW 60000
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#define PD_MAX_CURRENT_MA 3000
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#define PD_MAX_VOLTAGE_MV 20000
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#endif /* __USB_PD_CONFIG_H */
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