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Flash read,erase and write should access SPI flash and not read SRAM MAPPED location. flashrom -p and Software sync use the same flash functions to perform flashread,flashearse and flashwrite.So these functions should be reading RW image starting address offset.Address offset sent by host should not depend on the actual SPI flash as the EC code handles the right offset to program the ec.bin(via flashrom -p) and RW image only via software sync. BUG=chrome-os-partner:38103 BRANCH=None TEST=flashrom -p options tested to read and update ec.bin Change-Id: I3fb16accf3e05eaa3469a8a589962164574d5fb2 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/269231 Reviewed-by: Shawn N <shawnn@chromium.org>