wxjstz d277960eb8 riscv: Update register address ...

I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.

Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

2017-09-26 16:50:36 +00:00

..

arm

src/arch: Fix checkpatch warning: no spaces at the start of a line

2017-07-25 14:26:30 +00:00

arm64

arch/arm: Correct checkpatch errors

2017-06-02 18:30:53 +02:00

mips

arch/*: Update Kconfig symbol usage

2017-07-07 16:05:16 +00:00

power8

Rename __attribute__((packed)) --> __packed

2017-07-13 19:45:59 +00:00

riscv

riscv: Update register address

2017-09-26 16:50:36 +00:00

x86

arch/x86: Add ebda read/write functions into EBDA library

2017-09-22 15:29:38 +00:00