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90afebac64
BUG=chrome-os-partner:10880 TEST=boot EC; should stay in RO and not do signature check (verify via debug console output) Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I831aa91f8273bc7fb1a624cf36d9f21d52d8f3d8 Reviewed-on: https://gerrit.chromium.org/gerrit/26115 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Randall Spangler <rspangler@chromium.org>
107 lines
3.8 KiB
C
107 lines
3.8 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CHIP_CONFIG_H
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#define __CROS_EC_CHIP_CONFIG_H
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/* 16.000 Mhz internal oscillator frequency (PIOSC) */
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#define INTERNAL_CLOCK 16000000
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 132
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/* Debug UART parameters for panic message */
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#define CONFIG_UART_ADDRESS 0x4000c000
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#define CONFIG_UART_DR_OFFSET 0x00
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#define CONFIG_UART_SR_OFFSET 0x18
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#define CONFIG_UART_SR_TXEMPTY 0x80
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/****************************************************************************/
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/* Memory mapping */
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE 0x00008000
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/* System stack size */
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#define CONFIG_STACK_SIZE 4096
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#define CONFIG_FLASH_BASE 0x00000000
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#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
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/* This is the physical size of the flash on the chip. We'll reserve one bank
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* in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
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* doesn't support a write-protect pin, and if we make the write-protection
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* permanent, it can't be undone easily enough to support RMA. */
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#define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
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/* This is the size that we pretend we have. This is what flashrom expects,
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* what the FMAP reports, and what size we build images for. */
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#define CONFIG_FLASH_SIZE (CONFIG_FLASH_PHYSICAL_SIZE - CONFIG_FLASH_BANK_SIZE)
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/****************************************************************************/
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/* Define our flash layout. */
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/* The EC needs its own region for run-time vboot stuff. We can put
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* that up at the top */
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#define CONFIG_SECTION_ROLLBACK_SIZE (1 * CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_SECTION_ROLLBACK_OFF (CONFIG_FLASH_SIZE \
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- CONFIG_FLASH_ROLLBACK_SIZE)
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/* Then there are the three major sections. */
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#define CONFIG_SECTION_RO_SIZE (40 * CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_SECTION_RO_OFF CONFIG_FLASH_BASE
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#define CONFIG_SECTION_A_SIZE (40 * CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_SECTION_A_OFF (CONFIG_SECTION_RO_OFF \
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+ CONFIG_SECTION_RO_SIZE)
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#define CONFIG_SECTION_B_SIZE (40 * CONFIG_FLASH_BANK_SIZE)
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#define CONFIG_SECTION_B_OFF (CONFIG_SECTION_A_OFF \
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+ CONFIG_SECTION_A_SIZE)
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/* The top of each section will hold the vboot stuff, since the firmware vector
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* table has to go at the start. The root key will fit in 2K, but the vblocks
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* need 4K. */
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#define CONFIG_VBOOT_ROOTKEY_SIZE 0x800
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#define CONFIG_VBLOCK_SIZE 0x1000
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/* RO: firmware (+ FMAP), root keys */
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#define CONFIG_FW_RO_OFF CONFIG_SECTION_RO_OFF
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#define CONFIG_FW_RO_SIZE (CONFIG_SECTION_RO_SIZE \
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- CONFIG_VBOOT_ROOTKEY_SIZE)
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#define CONFIG_VBOOT_ROOTKEY_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
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/* A: firmware, vblock */
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#define CONFIG_FW_A_OFF CONFIG_SECTION_A_OFF
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#define CONFIG_FW_A_SIZE (CONFIG_SECTION_A_SIZE \
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- CONFIG_VBLOCK_SIZE)
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#define CONFIG_VBLOCK_A_OFF (CONFIG_FW_A_OFF + CONFIG_FW_A_SIZE)
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/* B: firmware, vblock */
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#define CONFIG_FW_B_SIZE (CONFIG_SECTION_B_SIZE \
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- CONFIG_VBLOCK_SIZE)
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#define CONFIG_FW_B_OFF (CONFIG_SECTION_A_OFF \
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+ CONFIG_SECTION_A_SIZE)
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#define CONFIG_VBLOCK_B_OFF (CONFIG_FW_B_OFF + CONFIG_FW_B_SIZE)
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/****************************************************************************/
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/* Customize the build */
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/* Build with assertions and debug messages */
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#define CONFIG_DEBUG
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_EEPROM
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#define CONFIG_FLASH
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#define CONFIG_FPU
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#define CONFIG_I2C
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/* Compile for running from RAM instead of flash */
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/* #define COMPILE_FOR_RAM */
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#endif /* __CROS_EC_CHIP_CONFIG_H */
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