mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-05 22:41:44 +00:00
b1bb8314bd
(And add STM32 support for disabling interrupts before reset, which got missed before.) Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7470 TEST=from console, "reboot", then "reboot hard" Change-Id: Ib98792abc0c91a01e2230b419fc876052380655a
127 lines
2.8 KiB
C
127 lines
2.8 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* System module for Chrome EC : hardware specific implementation */
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#include "cpu.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "version.h"
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static void check_reset_cause(void)
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{
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enum system_reset_cause_t reset_cause = SYSTEM_RESET_UNKNOWN;
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uint32_t raw_cause = STM32_RCC_CSR;
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/* Clear the hardware reset cause by setting the RMVF bit */
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STM32_RCC_CSR |= 1 << 24;
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if (raw_cause & 0x60000000) {
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/* IWDG pr WWDG */
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reset_cause = SYSTEM_RESET_WATCHDOG;
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} else if (raw_cause & 0x10000000) {
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reset_cause = SYSTEM_RESET_SOFT;
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} else if (raw_cause & 0x08000000) {
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reset_cause = SYSTEM_RESET_POWER_ON;
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} else if (raw_cause & 0x04000000) {
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reset_cause = SYSTEM_RESET_RESET_PIN;
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} else if (raw_cause & 0xFE000000) {
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reset_cause = SYSTEM_RESET_OTHER;
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}
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system_set_reset_cause(reset_cause);
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}
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void system_hibernate(uint32_t seconds, uint32_t microseconds)
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{
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/* we are going to hibernate ... */
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while (1)
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/* NOT IMPLEMENTED */;
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}
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int system_pre_init(void)
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{
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/* enable clock on Power module */
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STM32_RCC_APB1ENR |= 1 << 28;
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/* Enable access to RCC CSR register and RTC backup registers */
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STM32_PWR_CR |= 1 << 8;
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/* switch on LSI */
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STM32_RCC_CSR |= 1 << 0;
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/* Wait for LSI to be ready */
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while (!(STM32_RCC_CSR & (1 << 1)))
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;
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/* re-configure RTC if needed */
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#if defined(CHIP_VARIANT_stm32l15x)
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if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
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/* the RTC settings are bad, we need to reset it */
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STM32_RCC_CSR |= 0x00800000;
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/* Enable RTC and use LSI as clock source */
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STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
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}
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#elif defined(CHIP_VARIANT_stm32f100)
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if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) {
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/* the RTC settings are bad, we need to reset it */
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STM32_RCC_BDCR |= 0x00010000;
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/* Enable RTC and use LSI as clock source */
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STM32_RCC_BDCR = (STM32_RCC_BDCR & ~0x00018300) | 0x00008200;
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}
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#else
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#error "Unsupported chip variant"
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#endif
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check_reset_cause();
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return EC_SUCCESS;
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}
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void system_reset(int is_hard)
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{
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/* Disable interrupts to avoid task swaps during reboot */
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interrupt_disable();
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/* TODO: (crosbug.com/p/7470) support hard boot; this is a
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* soft boot. */
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CPU_NVIC_APINT = 0x05fa0004;
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/* Spin and wait for reboot; should never return */
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while (1)
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;
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}
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int system_set_scratchpad(uint32_t value)
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{
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STM32_RTC_BACKUP(0) = value;
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return EC_SUCCESS;
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}
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uint32_t system_get_scratchpad(void)
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{
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return STM32_RTC_BACKUP(0);
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}
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const char *system_get_chip_vendor(void)
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{
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return "stm";
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}
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const char *system_get_chip_name(void)
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{
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return STRINGIFY(CHIP_VARIANT);
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}
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const char *system_get_chip_revision(void)
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{
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return "";
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}
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