Etienne Carriere d56a846121 ARMv7: introduce Cortex-A5 ...

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

2017-11-08 13:49:45 +01:00

..

aarch32

Exit early if size zero for cache helpers

2017-06-21 17:46:28 +01:00

aarch64

Introduce functions to disable the MMU in EL1

2017-10-17 12:02:37 +01:00

compiler-rt

Import ctzdi2.c from LLVM compiler-rt

2017-07-26 09:28:23 +01:00

cpus

ARMv7: introduce Cortex-A5

2017-11-08 13:49:45 +01:00

el3_runtime

aarch64: Add PubSub events to capture security state transitions

2017-10-31 10:33:27 +00:00

libfdt

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

locks

ARMv7 does not support STL instruction

2017-11-08 13:49:29 +01:00

optee

Add Trusted OS extra image parsing support for ARM standard platforms

2017-08-09 18:06:05 +08:00

pmf

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

psci

PSCI: Publish CPU ON event

2017-10-23 08:15:11 +01:00

semihosting

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stack_protector

Use SPDX license identifiers

2017-05-03 09:39:28 +01:00

stdlib

Use standard UNIX file:line format in assert

2017-07-19 05:57:40 +01:00

utils

Add mem_region utility functions

2017-09-25 13:32:20 +01:00

xlat_tables

Set TCR_EL1.EPD1 bit to 1

2017-09-21 11:57:11 +01:00

xlat_tables_v2

xlat: Introduce API to change memory attributes of a region

2017-10-17 12:02:36 +01:00