Duncan Laurie d82caded48 baytrail: Add header include wrapper and offset define ...

Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode

Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5014
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

2014-05-12 22:08:15 +02:00

..

arch

SeaBIOS: Fix cpp use

2014-05-11 08:51:54 +02:00

console

console: Fix UART selection prompt

2014-04-30 23:47:28 +02:00

cpu

Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT

2014-05-10 11:27:25 +02:00

device

Introduce stage-specific architecture for coreboot

2014-05-06 20:23:31 +02:00

drivers

Intel FSP: add a shared set of functions for the FSP

2014-05-09 21:35:56 +02:00

ec

baytrail: Basic DPTF framework

2014-05-09 05:42:52 +02:00

include

ramstage_cache: allow ramstage usage add valid helper

2014-05-10 06:31:45 +02:00

lib

ramstage_cache: allow ramstage usage add valid helper

2014-05-10 06:31:45 +02:00

mainboard

superio/ite/it8718f: Remove hard coding from romstage

2014-05-12 17:43:46 +02:00

northbridge

cougar_canyon2: Switch CPU/NB/SB to the shared FSP code

2014-05-09 21:36:12 +02:00

soc

baytrail: Add header include wrapper and offset define

2014-05-12 22:08:15 +02:00

southbridge

cougar_canyon2: Switch CPU/NB/SB to the shared FSP code

2014-05-09 21:36:12 +02:00

superio

superio/ite/it8718f: Remove hard coding from romstage

2014-05-12 17:43:46 +02:00

vendorcode

Declare get_write_protect_state() without ChromeOS

2014-05-08 16:25:30 +02:00

Kconfig

Arch-level Kconfig menu cleanup

2014-05-10 14:32:26 +02:00