Siva Durga Prasad Paladugu d9710aeb03 aarch64: zynqmp: Add new Ids for RFSoC ...

Add new id codes for RFSoC's.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2018-05-17 15:12:52 +05:30

..

arm

Merge pull request #1387 from vishwanathahg/sgi575/core_pos_calc

2018-05-16 15:23:18 +01:00

common

Fix build error with correct format string

2018-05-15 17:05:36 +01:00

compat

Do not enable SVE on pre-v8.2 platforms

2017-11-30 17:45:23 +00:00

hisilicon

Merge pull request #1361 from vchong/tool_add_img

2018-05-01 17:12:51 +01:00

layerscape

layerscape: fix integer handling issues

2018-04-11 12:12:24 +00:00

mediatek

Fix pointer type mismatch of handlers

2018-04-27 18:35:02 +09:00

nvidia/tegra

types: use int-ll64 for both aarch32 and aarch64

2018-04-27 18:35:02 +09:00

qemu

Merge pull request #1334 from michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console

2018-04-03 11:59:55 +01:00

rockchip

Merge pull request #1255 from masahir0y/int-ll64

2018-05-01 15:06:56 +01:00

rpi3

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

2018-03-29 13:20:05 +01:00

socionext/uniphier

plat: fix switch statements to comply with MISRA rules

2018-03-26 12:43:05 +01:00

xilinx/zynqmp

aarch64: zynqmp: Add new Ids for RFSoC

2018-05-17 15:12:52 +05:30