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da185c1702
Provides a minimal API for coordinating with the SoC for bringing up the secondary CPUs. There's no eventloop or dispatcher currently nor does it do anything proper when one of the secondary CPUs are brought up. Those decisions are deferred to the SoC. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu using this API. Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376 Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214775 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <arch/exception.h>
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#include <arch/mmu.h>
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#include <arch/stages.h>
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/*
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* This variable holds entry point for CPUs starting up. Before the other
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* CPUs are brought up this value will change to provide the secondary
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* code path.
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*/
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void (*c_entry)(void) = &arm64_init;
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void __attribute__((weak)) arm64_soc_init(void)
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{
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/* Default weak implementation does nothing. */
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}
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void __attribute__((weak)) soc_secondary_cpu_init(void)
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{
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/* Default weak implementation does nothing. */
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}
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static void seed_stack(void)
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{
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char *stack_begin;
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uint64_t *slot;
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int i;
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int size;
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stack_begin = cpu_get_stack(smp_processor_id());
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stack_begin -= CONFIG_STACK_SIZE;
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slot = (void *)stack_begin;
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/* Pad out 256 bytes for current usage. */
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size = CONFIG_STACK_SIZE - 256;
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size /= sizeof(*slot);
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for (i = 0; i < size; i++)
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*slot++ = 0xdeadbeefdeadbeefULL;
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}
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void arm64_init(void)
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{
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seed_stack();
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arm64_soc_init();
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main();
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}
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static void secondary_cpu_start(void)
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{
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mmu_enable();
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exception_hwinit();
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soc_secondary_cpu_init();
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/*
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* TODO(adurbin): need a proper place to park the CPUs. Currently
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* assuming SoC code does the appropriate thing.
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*/
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while (1);
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}
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extern void arm64_cpu_startup(void);
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void *prepare_secondary_cpu_startup(void)
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{
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c_entry = &secondary_cpu_start;
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dcache_clean_invalidate_by_mva(c_entry, sizeof(c_entry));
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return &arm64_cpu_startup;
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}
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