mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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After every reboot, we were resetting the write protect and console lock states back to default. With this change the wp and lock states will be preserved through deep sleep. They will still be reset on any other type of reboot (like Power On reset or panic). The states are also cleared if the system detects a rollback even when booting from the deep sleep. With this patch it is going to be impossible to remove hardware write protection guarding writes into AP and EC firmware flash, unless the cr50 console is unlocked. Locking the console would reinstate hardware write protection automatically even if it was disabled when the console was unlocked. Two long life scratch register 1 bits are used to keep the console and write protect states over resets. To make code cleaner bitmap assignments of the long life scratch register is put in its own include file. BUG=chrome-os-partner:58961 BRANCH=none TEST=manual On prod/dev images verify that the default wp and console lock states are still correct. change the lock and write protect states from the default and verify they are preserved through deep sleep. reboot cr50 and make sure that they are reset. unlock the console and enable flash writes, then set fallback counter on cr50 to the value of 6 (rw 0x40000128 1; rw 0x4000012c 6) and put the AP into deep sleep by hitting Alt-H-VolUp. In five minutes press the power button on the device to bring it back from s5. Observe cr50 fall back to an older image and console lock and wp disabled. Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420812 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
441 lines
12 KiB
C
441 lines
12 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "config.h"
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#include "console.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "flash.h"
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#include "printf.h"
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#include "registers.h"
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#include "signed_header.h"
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#include "system.h"
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#include "task.h"
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#include "version.h"
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static void check_reset_cause(void)
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{
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uint32_t g_rstsrc = GR_PMU_RSTSRC;
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uint32_t flags = 0;
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/* Clear the reset source now we have recorded it */
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GR_PMU_CLRRST = 1;
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if (g_rstsrc & GC_PMU_RSTSRC_POR_MASK) {
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/* If power-on reset is true, that's the only thing */
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system_set_reset_flags(RESET_FLAG_POWER_ON);
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return;
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}
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/* Low-power exit (ie, wake from deep sleep) */
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if (g_rstsrc & GC_PMU_RSTSRC_EXIT_MASK) {
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/* This register is cleared by reading it */
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uint32_t g_exitpd = GR_PMU_EXITPD_SRC;
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flags |= RESET_FLAG_HIBERNATE;
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if (g_exitpd & GC_PMU_EXITPD_SRC_PIN_PD_EXIT_MASK)
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flags |= RESET_FLAG_WAKE_PIN;
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if (g_exitpd & GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_MASK)
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flags |= RESET_FLAG_USB_RESUME;
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if (g_exitpd & (GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK |
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GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK))
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flags |= RESET_FLAG_RTC_ALARM;
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if (g_exitpd & GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_MASK)
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flags |= RESET_FLAG_RDD;
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if (g_exitpd & GC_PMU_EXITPD_SRC_RBOX_WAKEUP_MASK)
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flags |= RESET_FLAG_RBOX;
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}
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if (g_rstsrc & GC_PMU_RSTSRC_SOFTWARE_MASK)
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flags |= RESET_FLAG_HARD;
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if (g_rstsrc & GC_PMU_RSTSRC_SYSRESET_MASK)
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flags |= RESET_FLAG_SOFT;
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if (g_rstsrc & GC_PMU_RSTSRC_FST_BRNOUT_MASK)
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flags |= RESET_FLAG_BROWNOUT;
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/*
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* GC_PMU_RSTSRC_WDOG and GC_PMU_RSTSRC_LOCKUP are considered security
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* threats. They won't show up as a direct reset cause.
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*/
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if (g_rstsrc & GC_PMU_RSTSRC_SEC_THREAT_MASK)
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flags |= RESET_FLAG_SECURITY;
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if (g_rstsrc && !flags)
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flags |= RESET_FLAG_OTHER;
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system_set_reset_flags(flags);
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}
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void system_pre_init(void)
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{
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check_reset_cause();
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/*
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* This SoC supports dual "RO" bootloader images. The bootloader locks
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* the running RW image (us) before jumping to it, but we want to be
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* sure the active bootloader is also locked. Any images updates must
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* go into an inactive image location. If it's already locked, this has
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* no effect.
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*/
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GREG32(GLOBALSEC, FLASH_REGION0_CTRL_CFG_EN) = 0;
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}
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void system_reset(int flags)
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{
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/* TODO: Do we need to handle SYSTEM_RESET_PRESERVE_FLAGS? Doubtful. */
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/* TODO(crosbug.com/p/47289): handle RESET_FLAG_WATCHDOG */
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/* Disable interrupts to avoid task swaps during reboot */
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interrupt_disable();
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#ifdef BOARD_CR50
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/*
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* On CR50 we want every reset be hard reset, causing the entire
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* chromebook to reboot: we don't want the TPM reset while the AP
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* stays up.
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*/
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GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY;
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#else
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if (flags & SYSTEM_RESET_HARD) {
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/* Reset the full microcontroller */
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GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY;
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} else {
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/* Soft reset is also fairly hard, and requires
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* permission registers to be reset to their initial
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* state. To accomplish this, first register a wakeup
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* timer and then enter lower power mode. */
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/* Low speed timers continue to run in low power mode. */
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GREG32(TIMELS, TIMER1_CONTROL) = 0x1;
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/* Wait for this long. */
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GREG32(TIMELS, TIMER1_LOAD) = 1;
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/* Setup wake-up on Timer1 firing. */
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GREG32(PMU, EXITPD_MASK) =
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GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK;
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/* All the components to power cycle. */
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GREG32(PMU, LOW_POWER_DIS) =
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GC_PMU_LOW_POWER_DIS_VDDL_MASK |
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GC_PMU_LOW_POWER_DIS_VDDIOF_MASK |
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GC_PMU_LOW_POWER_DIS_VDDXO_MASK |
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GC_PMU_LOW_POWER_DIS_JTR_RC_MASK;
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/* Start low power sequence. */
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REG_WRITE_MLV(GREG32(PMU, LOW_POWER_DIS),
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GC_PMU_LOW_POWER_DIS_START_MASK,
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GC_PMU_LOW_POWER_DIS_START_LSB,
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1);
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}
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#endif /* ^^^^^^^ BOARD_CR50 Not defined */
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/* Wait for reboot; should never return */
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asm("wfi");
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}
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const char *system_get_chip_vendor(void)
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{
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return "g";
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}
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const char *system_get_chip_name(void)
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{
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return "cr50";
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}
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const char *system_get_chip_revision(void)
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{
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int build_date = GR_SWDP_BUILD_DATE;
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int build_time = GR_SWDP_BUILD_TIME;
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if ((build_date != GC_SWDP_BUILD_DATE_DEFAULT) ||
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(build_time != GC_SWDP_BUILD_TIME_DEFAULT))
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return " BUILD MISMATCH!";
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switch (GREAD_FIELD(PMU, CHIP_ID, REVISION)) {
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case 3:
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return "B1";
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case 4:
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return "B2";
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}
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return "B?";
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}
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/* TODO(crosbug.com/p/33822): Where can we store stuff persistently? */
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int system_get_vbnvcontext(uint8_t *block)
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{
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return 0;
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}
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int system_set_vbnvcontext(const uint8_t *block)
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{
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return 0;
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}
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enum system_image_copy_t system_get_ro_image_copy(void)
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{
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/*
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* The bootrom protects the selected bootloader with REGION0,
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* so we should be able to identify the active RO by seeing which one
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* is protected.
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*/
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switch (GREG32(GLOBALSEC, FLASH_REGION0_BASE_ADDR)) {
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case CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF:
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return SYSTEM_IMAGE_RO;
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case CONFIG_PROGRAM_MEMORY_BASE + CHIP_RO_B_MEM_OFF:
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return SYSTEM_IMAGE_RO_B;
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}
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return SYSTEM_IMAGE_UNKNOWN;
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}
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/*
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* The RW images contain version strings. The RO images don't, so we'll make
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* some here.
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*/
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#define MAX_RO_VER_LEN 48
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static char vers_str[MAX_RO_VER_LEN];
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const char *system_get_version(enum system_image_copy_t copy)
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{
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const struct version_struct *v;
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const struct SignedHeader *h;
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enum system_image_copy_t this_copy;
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uintptr_t vaddr, delta;
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switch (copy) {
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case SYSTEM_IMAGE_RO:
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case SYSTEM_IMAGE_RO_B:
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/* The RO header is the first thing in each flash half */
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vaddr = get_program_memory_addr(copy);
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if (vaddr == INVALID_ADDR)
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break;
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h = (const struct SignedHeader *)vaddr;
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/* Use some fields from the header for the version string */
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snprintf(vers_str, MAX_RO_VER_LEN, "%d.%d.%d/%08x",
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h->epoch_, h->major_, h->minor_, h->img_chk_);
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return vers_str;
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case SYSTEM_IMAGE_RW:
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case SYSTEM_IMAGE_RW_B:
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/*
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* This function isn't part of any RO image, so we must be in a
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* RW image. If the current image is the one we're asked for,
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* we can just return our version string.
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*/
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this_copy = system_get_image_copy();
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vaddr = get_program_memory_addr(this_copy);
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h = (const struct SignedHeader *)vaddr;
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if (copy == this_copy) {
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snprintf(vers_str, sizeof(vers_str), "%d.%d.%d/%s",
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h->epoch_, h->major_, h->minor_,
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version_data.version);
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return vers_str;
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}
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/*
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* We want the version of the other RW image. The linker script
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* puts the version string right after the reset vectors, so
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* it's at the same relative offset. Measure that offset here.
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*/
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delta = (uintptr_t)&version_data - vaddr;
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/* Now look at that offset in the requested image */
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vaddr = get_program_memory_addr(copy);
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if (vaddr == INVALID_ADDR)
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break;
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h = (const struct SignedHeader *)vaddr;
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vaddr += delta;
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v = (const struct version_struct *)vaddr;
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/*
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* Make sure the version struct cookies match before returning
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* the version string.
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*/
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if (v->cookie1 == version_data.cookie1 &&
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v->cookie2 == version_data.cookie2 &&
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h->magic) { /* Corrupted header's magic is set to zero. */
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snprintf(vers_str, sizeof(vers_str), "%d.%d.%d/%s",
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h->epoch_, h->major_, h->minor_, v->version);
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return vers_str;
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}
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default:
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break;
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}
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return "Error";
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}
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#ifdef BOARD_CR50
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void system_clear_retry_counter(void)
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{
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GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 1);
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GREG32(PMU, LONG_LIFE_SCRATCH0) = 0;
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GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 0);
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}
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/*
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* Check which of the two cr50 RW images is newer, return true if the first
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* image is no older than the second one.
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*
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* Note that RO and RW images use the same header structure. When deciding
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* which image to run, the boot ROM ignores the timestamp, but the cros loader
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* considers the timestamp if all other fields are equal.
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*/
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static int a_is_newer_than_b(const struct SignedHeader *a,
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const struct SignedHeader *b)
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{
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if (a->epoch_ != b->epoch_)
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return a->epoch_ > b->epoch_;
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if (a->major_ != b->major_)
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return a->major_ > b->major_;
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if (a->minor_ != b->minor_)
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return a->minor_ > b->minor_;
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/* This comparison is not made by ROM. */
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if (a->timestamp_ != b->timestamp_)
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return a->timestamp_ > b->timestamp_;
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return 1; /* All else being equal, consider A to be newer. */
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}
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/*
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* Corrupt the 'magic' field of the passed in header. This prevents the
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* apparently failing image from being considered as a candidate to load and
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* run on the following reboots.
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*/
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static int corrupt_header(volatile struct SignedHeader *header)
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{
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int rv;
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const char zero[4] = {}; /* value to write to magic. */
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/* Enable RW access to the other header. */
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GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) = (uint32_t) header;
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GREG32(GLOBALSEC, FLASH_REGION6_SIZE) = 1023;
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GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, EN, 1);
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GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, RD_EN, 1);
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GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 1);
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ccprintf("%s: RW fallback must have happened, magic at %p before: %x\n",
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__func__, &header->magic, header->magic);
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rv = flash_physical_write((intptr_t)&header->magic -
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CONFIG_PROGRAM_MEMORY_BASE,
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sizeof(zero), zero);
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/* Disable W access to the other header. */
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GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 0);
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ccprintf("%s: magic after: %x\n",
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__func__, header->magic);
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return rv;
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}
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/*
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* Value of the retry counter which, if exceeded, indicates that the currently
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* running RW image is not well and is rebooting before bringing the system
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* manages to come up.
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*/
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#define RW_BOOT_MAX_RETRY_COUNT 5
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/*
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* Check if the current running image is newer. Set the passed in pointer, if
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* supplied, to point to the newer image in case the running image is the
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* older one.
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*/
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static int current_image_is_newer(struct SignedHeader **newer_image)
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{
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struct SignedHeader *me, *other;
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if (system_get_image_copy() == SYSTEM_IMAGE_RW) {
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me = (struct SignedHeader *)
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get_program_memory_addr(SYSTEM_IMAGE_RW);
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other = (struct SignedHeader *)
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get_program_memory_addr(SYSTEM_IMAGE_RW_B);
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} else {
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me = (struct SignedHeader *)
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get_program_memory_addr(SYSTEM_IMAGE_RW_B);
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other = (struct SignedHeader *)
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get_program_memory_addr(SYSTEM_IMAGE_RW);
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}
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if (a_is_newer_than_b(me, other))
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return 1;
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if (newer_image)
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*newer_image = other;
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return 0;
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}
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int system_rollback_detected(void)
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{
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return !current_image_is_newer(NULL);
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}
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int system_process_retry_counter(void)
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{
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unsigned retry_counter;
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struct SignedHeader *newer_image;
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retry_counter = GREG32(PMU, LONG_LIFE_SCRATCH0);
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system_clear_retry_counter();
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ccprintf("%s:retry counter %d\n", __func__, retry_counter);
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if (retry_counter <= RW_BOOT_MAX_RETRY_COUNT)
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return EC_SUCCESS;
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if (current_image_is_newer(&newer_image)) {
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ccprintf("%s: "
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"this is odd, I am newer, but retry counter was %d\n",
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__func__, retry_counter);
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return EC_SUCCESS;
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}
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/*
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* let's corrupt the newer image so that the next restart is happening
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* straight into the current version.
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*/
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return corrupt_header(newer_image);
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}
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int system_rolling_reboot_suspected(void)
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{
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if (GREG32(PMU, LONG_LIFE_SCRATCH0) > 50) {
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/*
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* The chip has restarted 50 times without the restart counter
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* cleared. There must be something wrong going, the chip is
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* likely in rolling reboot.
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*/
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ccprintf("%s: Try powercycling to clear this condition.\n",
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__func__);
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return 1;
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}
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return 0;
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}
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#endif
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/* Prepend header version to the current image's build info. */
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const char *system_get_build_info(void)
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{
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static char combined_build_info[150];
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if (!*combined_build_info) {
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const struct SignedHeader *me;
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me = (struct SignedHeader *)
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get_program_memory_addr(system_get_image_copy());
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snprintf(combined_build_info, sizeof(combined_build_info),
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"%d.%d.%d/%s",
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me->epoch_, me->major_, me->minor_, build_info);
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}
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return combined_build_info;
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}
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