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https://github.com/Telecominfraproject/OpenCellular.git
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1d916d7c6b
We'd defined them in a number of different files. This moves definitions to timer.h, and uses them everywhere we have large delays (since 10*SECOND is less typo-prone than 10000000). Also add msleep() and sleep() inline functions. No need for mdelay() or delay(), since any delays that long should use sleep funcs instead of spin-waiting. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; taskinfo displays similar numbers to before Change-Id: I2a92a9f10f46b6b7b6571759b1f8ab4ecfbf8259 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36726
112 lines
2.5 KiB
C
112 lines
2.5 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver */
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#include "clock.h"
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#include "common.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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void __hw_clock_event_set(uint32_t deadline)
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{
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/* set the match on the deadline */
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LM4_TIMER_TAMATCHR(6) = 0xffffffff - deadline;
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/* Set the match interrupt */
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LM4_TIMER_IMR(6) |= 0x10;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return 0xffffffff - LM4_TIMER_TAMATCHR(6);
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}
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void __hw_clock_event_clear(void)
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{
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/* Disable the match interrupt */
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LM4_TIMER_IMR(6) &= ~0x10;
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}
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uint32_t __hw_clock_source_read(void)
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{
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return 0xffffffff - LM4_TIMER_TAV(6);
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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LM4_TIMER_TAV(6) = 0xffffffff - ts;
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}
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static void __hw_clock_source_irq(void)
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{
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uint32_t status = LM4_TIMER_RIS(6);
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/* Clear interrupt */
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LM4_TIMER_ICR(6) = status;
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/*
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* Find expired timers and set the new timer deadline; check the IRQ
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* status to determine if the free-running counter overflowed.
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*/
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process_timers(status & 0x01);
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}
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DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
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static void update_prescaler(void)
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{
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/*
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* Set the prescaler to increment every microsecond. This takes
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* effect immediately, because the TAILD bit in TAMR is clear.
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*/
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LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
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int __hw_clock_source_init(uint32_t start_t)
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{
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volatile uint32_t scratch __attribute__((unused));
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/*
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* Use WTIMER0 (timer 6) configured as a free running counter with 1 us
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* period.
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*/
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/* Enable WTIMER0 clock */
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LM4_SYSTEM_RCGCWTIMER |= 1;
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/* wait 3 clock cycles before using the module */
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scratch = LM4_SYSTEM_RCGCWTIMER;
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/* Ensure timer is disabled : TAEN = TBEN = 0 */
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LM4_TIMER_CTL(6) &= ~0x101;
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/* Set overflow interrupt */
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LM4_TIMER_IMR(6) = 0x1;
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/* 32-bit timer mode */
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LM4_TIMER_CFG(6) = 4;
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/* Set initial prescaler */
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update_prescaler();
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/* Periodic mode, counting down */
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LM4_TIMER_TAMR(6) = 0x22;
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/* Use the full 32-bits of the timer */
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LM4_TIMER_TAILR(6) = 0xffffffff;
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/* Starts counting in timer A */
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LM4_TIMER_CTL(6) |= 0x1;
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/*
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* Override the count with the start value now that counting has
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* started.
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*/
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__hw_clock_source_set(start_t);
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/* Enable interrupt */
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task_enable_irq(LM4_IRQ_TIMERW0A);
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return LM4_IRQ_TIMERW0A;
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}
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