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93cc00fde1
This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Andes cores
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Process Status Word bits */
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#define PSW_GIE (1 << 0) /* Global Interrupt Enable */
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#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
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#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
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/* write Process Status Word privileged register */
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static inline void set_psw(uint32_t val)
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{
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asm volatile ("mtsr %0, $PSW" : : "r"(val));
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}
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/* read Process Status Word privileged register */
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static inline uint32_t get_psw(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $PSW" : "=r"(ret));
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return ret;
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}
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/* write Interruption Program Counter privileged register */
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static inline void set_ipc(uint32_t val)
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{
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asm volatile ("mtsr %0, $IPC" : : "r"(val));
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}
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/* read Interruption Program Counter privileged register */
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static inline uint32_t get_ipc(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $IPC" : "=r"(ret));
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return ret;
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}
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/* read Interruption Type privileged register */
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static inline uint32_t get_itype(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
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return ret;
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}
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/* Generic CPU core initialization */
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void cpu_init(void);
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#endif /* __CPU_H */
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