mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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3e844ec271
Fix zinger and keyborg to use correct event mask when timing out from task_wait_event(): TASK_EVENT_TIMER. On zinger, move storing the last event to after enabling interrupts. This gives an opportunity to interrupt handler to set the wake event. BUG=chrome-os-partner:30135 BRANCH=none TEST=load on zinger, and test PD communication with samus. notably tested sending rw_hash vdm from samus, which is known to cause zinger to retry the following ping transmit. The retry on the ping transmit uses task_wait_event(), and without this fix we were getting false wake events that had been stored up from the last rx received event. with this fix, the retry mechanism works. Change-Id: I9a6902ceaab49a00d3660f9813ca7761cf38f190 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213560 Reviewed-by: Todd Broch <tbroch@chromium.org>
140 lines
2.7 KiB
C
140 lines
2.7 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* tiny substitute of the runtime layer */
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#include "common.h"
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#include "cpu.h"
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#include "debug.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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volatile uint32_t last_event;
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timestamp_t get_time(void)
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{
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timestamp_t t;
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t.le.lo = STM32_TIM32_CNT(2);
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t.le.hi = 0;
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return t;
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}
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void udelay(unsigned us)
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{
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unsigned t0 = STM32_TIM32_CNT(2);
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while ((STM32_TIM32_CNT(2) - t0) < us)
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;
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}
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void task_enable_irq(int irq)
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{
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CPU_NVIC_EN(0) = 1 << irq;
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}
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void task_disable_irq(int irq)
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{
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CPU_NVIC_DIS(0) = 1 << irq;
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}
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void task_clear_pending_irq(int irq)
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{
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CPU_NVIC_UNPEND(0) = 1 << irq;
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}
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uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
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{
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last_event = event;
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return 0;
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}
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void tim2_interrupt(void)
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{
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STM32_TIM_DIER(2) = 0; /* disable match interrupt */
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task_clear_pending_irq(STM32_IRQ_TIM2);
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last_event = TASK_EVENT_TIMER;
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}
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DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
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uint32_t task_wait_event(int timeout_us)
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{
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uint32_t evt;
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asm volatile("cpsid i");
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/* the event already happened */
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if (last_event || !timeout_us) {
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evt = last_event;
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last_event = 0;
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asm volatile("cpsie i ; isb");
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return evt;
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}
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/* set timeout on timer */
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if (timeout_us > 0) {
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STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us;
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STM32_TIM_SR(2) = 0; /* clear match flag */
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STM32_TIM_DIER(2) = 2; /* match interrupt */
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}
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/* sleep until next interrupt */
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asm volatile("wfi");
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STM32_TIM_DIER(2) = 0; /* disable match interrupt */
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asm volatile("cpsie i ; isb");
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/* note: interrupt that woke us up will run here */
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evt = last_event;
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last_event = 0;
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return evt;
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}
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void cpu_reset(void)
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{
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/* Disable interrupts */
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asm volatile("cpsid i");
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/* reboot the CPU */
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CPU_NVIC_APINT = 0x05fa0004;
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/* Spin and wait for reboot; should never return */
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while (1)
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;
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}
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/**
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* Default exception handler, which reports a panic.
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*
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* Declare this as a naked call so we can extract the real LR and SP.
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*/
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void exception_panic(void) __attribute__((naked));
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void exception_panic(void)
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{
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asm volatile(
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#ifdef CONFIG_DEBUG_PRINTF
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"mov r0, %0\n"
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"mov r3, sp\n"
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"ldr r1, [r3, #6*4]\n" /* retrieve exception PC */
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"ldr r2, [r3, #5*4]\n" /* retrieve exception LR */
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"bl debug_printf\n"
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#endif
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"b cpu_reset\n"
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: : "r"("PANIC PC=%08x LR=%08x\n\n"));
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}
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void panic_reboot(void)
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{ /* for div / 0 */
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debug_printf("DIV0 PANIC\n\n");
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cpu_reset();
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}
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/* --- stubs --- */
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void __hw_timer_enable_clock(int n, int enable)
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{ /* Done in hardware init */ }
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void usleep(unsigned us)
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{ /* Used only as a workaround */ }
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