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68abc0f428
It would be really nice to be guaranteed to see watchdog warnings before we actually hit a watchdog reset even if something strange is going on with the CPU. Let's increase the margin between the timer and the independent so that the hardware watchdog is really hit as a last resort. It seems like a 1.6 second hardware watchdog wouldn't be the end of the world so let's bump that way rather than increasing the number of warnings. BRANCH=ToT BUG=chrome-os-partner:29162 TEST="waitms 1000" on EC console no longer ever reboots and "waitms 2000" usually does. Change-Id: Ic5e5ddec22fb8484cc7c552b19d3f2043c105d0c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204895 Reviewed-by: Randall Spangler <rspangler@chromium.org>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Chip config header file */
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* Memory mapping */
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#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
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#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
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extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
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#define CONFIG_FLASH_BASE ((uintptr_t)__host_flash)
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#define CONFIG_FLASH_BANK_SIZE 0x1000
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#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
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#define CONFIG_RAM_BASE 0x0 /* Not supported */
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#define CONFIG_RAM_SIZE 0x0 /* Not supported */
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/* Size of one firmware image in flash */
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#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
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#define CONFIG_FW_RO_OFF 0
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#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
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#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
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#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
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/*
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* Put this after RO to give RW more space and make RO write protect region
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* contiguous.
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*/
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#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
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#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
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/* Maximum number of deferrable functions */
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#define DEFERRABLE_MAX_COUNT 8
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 250
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* Do NOT use common panic code (designed to output information on the UART) */
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#undef CONFIG_COMMON_PANIC_OUTPUT
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/* Do NOT use common timer code which is designed for hardware counters. */
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#undef CONFIG_COMMON_TIMER
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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