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0f73a129b4
The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
18 lines
395 B
C
18 lines
395 B
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Set up the Cortex-M0 core
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*/
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#include "cpu.h"
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void cpu_init(void)
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{
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/* Catch unaligned access */
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CPU_NVIC_CCR |= CPU_NVIC_CCR_UNALIGN_TRAP;
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/* Set supervisor call (SVC) to priority 0 */
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CPU_NVIC_SHCSR2 = 0;
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}
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