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0f73a129b4
The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and definitions for Cortex-M0 processor
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
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#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
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#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400)
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/* System Control Block */
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/* SCB AIRCR : Application interrupt and reset control register */
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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/* SCB SCR : System Control Register */
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#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
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#define CPU_NVIC_CCR CPUREG(0xe000ed14)
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#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
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#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
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#define CPU_NVIC_CCR_UNALIGN_TRAP (1 << 3)
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/* Set up the cpu to detect faults */
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void cpu_init(void);
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#endif /* __CPU_H */
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