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0e402965fa
Currently, on stm32f cortex-m0 systems, interrupts are always being directed to the RO vector table. This can cause strange problems when running RW software because it is still calling IRQ handlers in the RO code. Unfortunately, on cortex-m0 the ability to specify the vector table location in flash (VTOR register) is optional, and stm32f0 parts do not have it. Instead, in order to run RW IRQ handlers, at init time, this CL copies the vector table from flash to the base address of SRAM (0x20000000), and then selects SRAM to be mapped to 0x00000000 where the core looks to find the vector table. BUG=none BRANCH=none TEST=Tested on zinger. - Verified that vector table is copied to SRAM by printing out 48 words from SRAM base address 0x20000000 in main() and verifying that it matches the vector table in flash in the disassembly. - Verified the vector table at SRAM 0x20000000 points to the RW handlers when in RW and the RO handlers when in RO. - Also printed out PC in one IRQ handler and verified it was in the appropriate section of code. Also, ran on samus_pd and did a sysjump RW to make sure at least one other system works. Change-Id: I22aff1b5e0de9b23fd3324f0cbe4f6c45a81967e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/210063 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
197 lines
5.1 KiB
ArmAsm
197 lines
5.1 KiB
ArmAsm
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Cortex-M0 CPU initialization
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*/
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#include "config.h"
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.section .text.vecttable
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.macro vector name
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.long \name\()_handler
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.weak \name\()_handler
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.set \name\()_handler, default_handler
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.endm
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.macro vector_irq number
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.if \number < CONFIG_IRQ_COUNT
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vector irq_\()\number
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.endif
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.endm
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/* Exceptions vector */
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vectors:
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.long stack_end @ initial stack pointer
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.long reset @ reset handler
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vector nmi @ NMI handler
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vector hard_fault @ HardFault handler
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vector mpu_fault @ MPU fault handler
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vector bus_fault @ Bus fault handler
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vector usage_fault @ Usage fault handler
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.long 0 @ reserved
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.long 0 @ reserved
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.long 0 @ reserved
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.long 0 @ reserved
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vector svc @ SWI
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vector debug @ Debug handler
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.long 0 @ reserved
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vector pendsv @ PendSV handler
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vector sys_tick @ SysTick handler
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vector_irq 0 @ IRQ 0 handler
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vector_irq 1 @ IRQ 1 handler
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vector_irq 2 @ IRQ 2 handler
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vector_irq 3 @ IRQ 3 handler
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vector_irq 4 @ IRQ 4 handler
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vector_irq 5 @ IRQ 5 handler
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vector_irq 6 @ IRQ 6 handler
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vector_irq 7 @ IRQ 7 handler
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vector_irq 8 @ IRQ 8 handler
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vector_irq 9 @ IRQ 9 handler
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vector_irq 10 @ IRQ 10 handler
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vector_irq 11 @ IRQ 11 handler
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vector_irq 12 @ IRQ 12 handler
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vector_irq 13 @ IRQ 13 handler
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vector_irq 14 @ IRQ 14 handler
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vector_irq 15 @ IRQ 15 handler
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vector_irq 16 @ IRQ 16 handler
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vector_irq 17 @ IRQ 17 handler
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vector_irq 18 @ IRQ 18 handler
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vector_irq 19 @ IRQ 19 handler
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vector_irq 20 @ IRQ 20 handler
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vector_irq 21 @ IRQ 21 handler
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vector_irq 22 @ IRQ 22 handler
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vector_irq 23 @ IRQ 23 handler
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vector_irq 24 @ IRQ 24 handler
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vector_irq 25 @ IRQ 25 handler
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vector_irq 26 @ IRQ 26 handler
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vector_irq 27 @ IRQ 27 handler
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vector_irq 28 @ IRQ 28 handler
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vector_irq 29 @ IRQ 29 handler
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vector_irq 30 @ IRQ 30 handler
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vector_irq 31 @ IRQ 31 handler
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#ifdef CHIP_FAMILY_STM32F0
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/* Allocate space for SRAM vector table at SRAM based address */
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.section .bss.vector_table
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sram_vtable: .skip (48*4)
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#endif
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.text
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.syntax unified
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.code 16
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.global reset
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.thumb_func
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reset:
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/*
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* Ensure we're in privileged mode with main stack. Necessary if
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* we've jumped directly here from another image after task_start().
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*/
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movs r0, #0 @ priv. mode / main stack / no floating point
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msr control, r0
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isb @ ensure the write is done
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/* Clear BSS */
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movs r0, #0
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ldr r1,_bss_start
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ldr r2,_bss_end
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bss_loop:
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str r0, [r1]
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adds r1, #4
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cmp r1, r2
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blt bss_loop
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#ifdef CHIP_FAMILY_STM32F0
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/*
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* STM32F0 parts don't have the VTOR register for relocating
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* the vector table. Instead, we must copy the vector table from
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* flash into SRAM.
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*/
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ldr r1, =vectors
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ldr r2, =sram_vtable
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movs r0, #0
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vtable_loop:
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ldr r3, [r1]
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str r3, [r2]
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adds r1, #4
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adds r2, #4
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adds r0, #1
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cmp r0, #48
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blt vtable_loop
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/* Set SYSCFG_CFGR1 mem_mode to load vector table from SRAM */
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movs r0, #3
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ldr r1, =0x40010000
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str r0, [r1]
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#else
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/* Set the vector table on our current code */
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ldr r1, =vectors
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ldr r2, =0xE000ED08 /* VTOR register in SCB*/
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str r1, [r2]
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#endif
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#ifndef COMPILE_FOR_RAM
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/* Copy initialized data to Internal RAM */
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ldr r0,_ro_end
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ldr r1,_data_start
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ldr r2,_data_end
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data_loop:
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ldr r3, [r0]
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adds r0, #4
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str r3, [r1]
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adds r1, #4
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cmp r1, r2
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blt data_loop
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#endif
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/*
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* Set stack pointer. Already done by Cortex-M hardware, but re-doing
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* this here allows software to jump directly to the reset vector.
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*/
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ldr r0, =stack_end
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mov sp, r0
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/* Jump to C code */
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bl main
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/* That should not return. If it does, loop forever. */
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fini_loop:
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b fini_loop
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/* Default exception handler */
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.thumb_func
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default_handler:
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ldr r0, =exception_panic
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bx r0
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.align 2
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_bss_start:
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.long __bss_start
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_bss_end:
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.long __bss_end
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_data_start:
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.long __data_start
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_data_end:
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.long __data_end
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_ro_end:
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.long __ro_end
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/* Dummy functions to avoid linker complaints */
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.global __aeabi_unwind_cpp_pr0
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.global __aeabi_unwind_cpp_pr1
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.global __aeabi_unwind_cpp_pr2
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__aeabi_unwind_cpp_pr0:
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__aeabi_unwind_cpp_pr1:
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__aeabi_unwind_cpp_pr2:
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bx lr
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/* Reserve space for system stack */
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.section .bss.system_stack
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stack_start:
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.space CONFIG_STACK_SIZE, 0
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stack_end:
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.global stack_end
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