mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-06 23:51:28 +00:00
2d25b40b75
We actually need to care about x, the PRI register is actually a list of registers (and we have code that uses some of the later ones). BUG=None, discovered while chrome-os-partner:33451 TEST=Change priorities of irqs(like UART over GPIO(spi_event)), note how they actually work and override each other as told BRANCH=None Change-Id: I9f5bf7ba9d4211f782ff260fbce17deb7c53a31f Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/236087 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
|
|
* Use of this source code is governed by a BSD-style license that can be
|
|
* found in the LICENSE file.
|
|
*
|
|
* Registers map and definitions for Cortex-M0 processor
|
|
*/
|
|
|
|
#ifndef __CPU_H
|
|
#define __CPU_H
|
|
|
|
#include <stdint.h>
|
|
|
|
/* Macro to access 32-bit registers */
|
|
#define CPUREG(addr) (*(volatile uint32_t*)(addr))
|
|
|
|
/* Nested Vectored Interrupt Controller */
|
|
#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
|
|
#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
|
|
#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
|
|
#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
|
|
#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
|
|
|
|
/* System Control Block */
|
|
|
|
/* SCB AIRCR : Application interrupt and reset control register */
|
|
#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
|
|
/* SCB SCR : System Control Register */
|
|
#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
|
|
#define CPU_NVIC_CCR CPUREG(0xe000ed14)
|
|
#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
|
|
#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
|
|
|
|
#define CPU_NVIC_CCR_UNALIGN_TRAP (1 << 3)
|
|
|
|
/* Set up the cpu to detect faults */
|
|
void cpu_init(void);
|
|
|
|
#endif /* __CPU_H */
|