mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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c54375df26
When starting up the Cr50 should check if this image is supposed to
run on a chip with the board ID value read from INFO1.
If it is not supposed to run on this chip, and there is no rollback
counter overflow, set the rollback counter to a value which will
trigger a rollback and reboot.
If rollback counter has already exceeded the threshold - set a flag
indicating that the image is running in the "mismatch" mode and
continue.
BRANCH=cr50
BUG=b:35586335
TEST=with the rest of the patches applied verified both falling back
to an older image and continuing running with the flag set if
rollback is not possible.
Change-Id: I58d97de61dc446aaf1dd06b6e2b6bb426c14a172
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/535977
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
257 lines
6.4 KiB
C
257 lines
6.4 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/*
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* The default watchdog timeout is 1.6 seconds, but there are some legitimate
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* flash-intensive TPM operations that actually take close to that long to
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* complete. Make sure we don't trigger the watchdog accidentally if the timing
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* is just a little off.
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*/
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#undef CONFIG_WATCHDOG_PERIOD_MS
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#define CONFIG_WATCHDOG_PERIOD_MS 5000
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/* Features that we don't want */
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#undef CONFIG_CMD_LID_ANGLE
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#undef CONFIG_CMD_POWERINDEBUG
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#undef CONFIG_DMA_DEFAULT_HANDLERS
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#undef CONFIG_FMAP
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#undef CONFIG_HIBERNATE
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#undef CONFIG_LID_SWITCH
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#undef CONFIG_CMD_SYSINFO
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#undef CONFIG_CMD_SYSJUMP
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#undef CONFIG_CMD_SYSLOCK
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#ifndef CR50_DEV
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/* Disable stuff that should only be in debug builds */
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#undef CONFIG_CMD_CRASH
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#undef CONFIG_CMD_MD
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#undef CONFIG_CMD_RW
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#undef CONFIG_CMD_SLEEPMASK
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#undef CONFIG_CMD_WAITMS
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#undef CONFIG_FLASH
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#endif
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/* Flash configuration */
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#undef CONFIG_FLASH_PSTATE
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#define CONFIG_WP_ALWAYS
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#define CONFIG_CMD_FLASH
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#define CONFIG_CRC8
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/* Non-volatile counter storage for U2F */
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#define CONFIG_FLASH_NVCOUNTER
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#define CONFIG_FLASH_NVCTR_SIZE CONFIG_FLASH_BANK_SIZE
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#define CONFIG_FLASH_NVCTR_BASE_A (CONFIG_PROGRAM_MEMORY_BASE + \
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CFG_TOP_A_OFF)
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#define CONFIG_FLASH_NVCTR_BASE_B (CONFIG_PROGRAM_MEMORY_BASE + \
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CFG_TOP_B_OFF)
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/* We're using TOP_A for partition 0, TOP_B for partition 1 */
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#define CONFIG_FLASH_NVMEM
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/* Offset to start of NvMem area from base of flash */
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#define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF + CONFIG_FLASH_NVCTR_SIZE)
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#define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF + CONFIG_FLASH_NVCTR_SIZE)
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/* Address of start of Nvmem area */
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#define CONFIG_FLASH_NVMEM_BASE_A (CONFIG_PROGRAM_MEMORY_BASE + \
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CONFIG_FLASH_NVMEM_OFFSET_A)
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#define CONFIG_FLASH_NVMEM_BASE_B (CONFIG_PROGRAM_MEMORY_BASE + \
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CONFIG_FLASH_NVMEM_OFFSET_B)
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/* Size partition in NvMem */
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#define NVMEM_PARTITION_SIZE (CFG_TOP_SIZE - CONFIG_FLASH_NVCTR_SIZE)
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/* Size in bytes of NvMem area */
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#define CONFIG_FLASH_NVMEM_SIZE (NVMEM_PARTITION_SIZE * NVMEM_NUM_PARTITIONS)
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/* Enable <key, value> variable support. */
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#define CONFIG_FLASH_NVMEM_VARS
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#define NVMEM_CR50_SIZE 272
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#define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE
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/* Go to sleep when nothing else is happening */
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#define CONFIG_LOW_POWER_IDLE
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/* Allow multiple concurrent memory allocations. */
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#define CONFIG_MALLOC
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/* Detect the states of other devices */
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#define CONFIG_DEVICE_STATE
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/* Enable debug cable detection */
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#define CONFIG_RDD
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/* USB configuration */
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#define CONFIG_USB
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#define CONFIG_USB_CONSOLE
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#define CONFIG_USB_I2C
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#define CONFIG_USB_INHIBIT_INIT
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#define CONFIG_USB_SELECT_PHY
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#define CONFIG_USB_SPI
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#define CONFIG_USB_SERIALNO
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#define DEFAULT_SERIALNO "0"
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#define CONFIG_STREAM_USART
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#define CONFIG_STREAM_USB
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#define CONFIG_STREAM_USART1
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#define CONFIG_STREAM_USART2
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/* Enable Case Closed Debugging */
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#define CONFIG_CASE_CLOSED_DEBUG
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#define CONFIG_USB_PID 0x5014
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#define CONFIG_USB_SELF_POWERED
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#undef CONFIG_USB_MAXPOWER_MA
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#define CONFIG_USB_MAXPOWER_MA 0
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/* Need to be able to bitbang the EC UART for updates through CCD. */
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#define CONFIG_UART_BITBANG
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/* Enable SPI Master (SPI) module */
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#define CONFIG_SPI_MASTER
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#define CONFIG_SPI_MASTER_NO_CS_GPIOS
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#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
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#define CONFIG_SPI_FLASH_PORT 0
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/* Enable SPI Slave (SPS) module */
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#define CONFIG_SPS
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#define CONFIG_TPM_SPS
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#define CONFIG_RBOX
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/* We don't need to send events to the AP */
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#undef CONFIG_HOSTCMD_EVENTS
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/* Make most commands restricted */
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#define CONFIG_CONSOLE_COMMAND_FLAGS
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#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
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#define CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT CMD_FLAG_RESTRICTED
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/* Include crypto stuff, both software and hardware. */
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#define CONFIG_DCRYPTO
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#define CONFIG_UPTO_SHA512
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#ifndef __ASSEMBLER__
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#include "gpio_signal.h"
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/* USB string indexes */
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enum usb_strings {
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USB_STR_DESC = 0,
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USB_STR_VENDOR,
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USB_STR_PRODUCT,
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USB_STR_VERSION,
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USB_STR_CONSOLE_NAME,
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USB_STR_BLOB_NAME,
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USB_STR_HID_KEYBOARD_NAME,
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USB_STR_AP_NAME,
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USB_STR_EC_NAME,
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USB_STR_UPGRADE_NAME,
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USB_STR_SPI_NAME,
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USB_STR_SERIALNO,
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USB_STR_I2C_NAME,
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USB_STR_COUNT
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};
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/* Device indexes */
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enum device_type {
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DEVICE_AP = 0,
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DEVICE_EC,
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DEVICE_SERVO,
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DEVICE_BATTERY_PRESENT,
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DEVICE_CCD_MODE,
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DEVICE_COUNT
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};
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/* NVMem variables. */
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enum nvmem_vars {
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NVMEM_VAR_CONSOLE_LOCKED = 0,
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NVMEM_VAR_TEST_VAR,
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NVMEM_VARS_COUNT
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};
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void board_configure_deep_sleep_wakepins(void);
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/* Interrupt handler */
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void tpm_rst_deasserted(enum gpio_signal signal);
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void device_state_on(enum gpio_signal signal);
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void post_reboot_request(void);
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void ec_tx_cr50_rx(enum gpio_signal signal);
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/* Special controls over EC and AP */
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void assert_sys_rst(void);
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void deassert_sys_rst(void);
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int is_sys_rst_asserted(void);
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void assert_ec_rst(void);
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void deassert_ec_rst(void);
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int is_ec_rst_asserted(void);
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int board_has_ap_usb(void);
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int board_use_plt_rst(void);
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int board_rst_pullup_needed(void);
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int board_tpm_uses_i2c(void);
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int board_tpm_uses_spi(void);
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int board_id_is_mismatched(void);
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#endif /* !__ASSEMBLER__ */
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/* USB interface indexes (use define rather than enum to expand them) */
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#define USB_IFACE_CONSOLE 0
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#define USB_IFACE_AP 1
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#define USB_IFACE_EC 2
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#define USB_IFACE_UPGRADE 3
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#define USB_IFACE_SPI 4
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#define USB_IFACE_I2C 5
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#define USB_IFACE_COUNT 6
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/* USB endpoint indexes (use define rather than enum to expand them) */
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#define USB_EP_CONTROL 0
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#define USB_EP_CONSOLE 1
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#define USB_EP_AP 2
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#define USB_EP_EC 3
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#define USB_EP_UPGRADE 4
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#define USB_EP_SPI 5
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#define USB_EP_I2C 6
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#define USB_EP_COUNT 7
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/* UART indexes (use define rather than enum to expand them) */
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#define UART_CR50 0
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#define UART_AP 1
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#define UART_EC 2
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#define UARTN UART_CR50
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#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_TPM))
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/* Nv Memory users */
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#ifndef __ASSEMBLER__
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enum nvmem_users {
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NVMEM_TPM = 0,
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NVMEM_CR50,
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NVMEM_NUM_USERS
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};
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#endif
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#define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50
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#define CONFIG_RW_B
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/* Firmware upgrade options. */
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#define CONFIG_NON_HC_FW_UPDATE
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#define CONFIG_USB_FW_UPDATE
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#define CONFIG_I2C
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#define CONFIG_I2C_MASTER
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#define CONFIG_I2C_SLAVE
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#define CONFIG_TPM_I2CS
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#define CONFIG_BOARD_ID_SUPPORT
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#define CONFIG_EXTENDED_VERSION_INFO
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#define I2C_PORT_MASTER 0
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#endif /* __CROS_EC_BOARD_H */
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