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a30bb73e78
BRANCH=None BUG=None Change-Id: Icfb20bff28a593c9058d67ad09f188c567b7401c Reviewed-on: https://chromium-review.googlesource.com/454240 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/*
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* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __EC_BOARD_CR50_SCRATCH_REG1_H
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#define __EC_BOARD_CR50_SCRATCH_REG1_H
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/*
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* Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives
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* all kinds of resets, it is cleared only on the Power ON event.
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*/
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#define BOARD_SLAVE_CONFIG_SPI (1 << 0) /* TPM uses SPI interface */
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#define BOARD_SLAVE_CONFIG_I2C (1 << 1) /* TPM uses I2C interface */
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#define BOARD_USB_AP (1 << 2) /* One of the USB PHYs is */
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/* connected to the AP */
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/*
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* The gaps are left to enusre backwards compatibility with the earliest cr50
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* code releases. It will be possible to safely reuse these gaps if and when the
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* rest of the bits are taken.
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*/
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/* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
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#define BOARD_NEEDS_SYS_RST_PULL_UP (1 << 5) /* Add a pullup to sys_rst_l */
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#define BOARD_USE_PLT_RESET (1 << 6) /* Use plt_rst_l instead of */
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/* sys_rst_l to monitor the */
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/* system resets */
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/* Bits to store write protect bit state across deep sleep and resets. */
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#define BOARD_WP_ASSERTED (1 << 8)
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#define BOARD_FORCING_WP (1 << 9)
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/*
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* Bit to signal to compatible RO to suppress its uart output.
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* Helps to reduce time to resume from deep sleep.
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*/
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#define BOARD_NO_RO_UART (1 << 10)
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/*
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* Macro to capture all properties related to board strapping pins. This must be
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* updated if additional strap related properties are added.
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*/
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#define BOARD_ALL_PROPERTIES (BOARD_SLAVE_CONFIG_SPI | BOARD_SLAVE_CONFIG_I2C \
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| BOARD_USB_AP | BOARD_NEEDS_SYS_RST_PULL_UP | BOARD_USE_PLT_RESET)
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#endif /* ! __EC_BOARD_CR50_SCRATCH_REG1_H */
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