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https://github.com/Telecominfraproject/OpenCellular.git
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81b2654dc9
Add console and usb_spi commands to enable or disable IOs to the socket, so that it will not be powered if a chip is inserted, and control reset and boot_cfg. BUG=b:36910757 BRANCH=None TEST=Check no voltage when socket is disabled. Full spiflash compatibility. Change-Id: Ie4ce0613a868030833abfdccd827acce2753dc6f Reviewed-on: https://chromium-review.googlesource.com/509072 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
193 lines
4.8 KiB
C
193 lines
4.8 KiB
C
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/*
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* Make sure we don't trigger the watchdog accidentally if the timing
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* is just a little off.
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*/
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#undef CONFIG_WATCHDOG_PERIOD_MS
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#define CONFIG_WATCHDOG_PERIOD_MS 5000
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#define CR50_DEV
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/* Features that we don't want */
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#undef CONFIG_CMD_LID_ANGLE
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#undef CONFIG_CMD_POWERINDEBUG
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#undef CONFIG_DMA_DEFAULT_HANDLERS
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#undef CONFIG_FMAP
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#undef CONFIG_HIBERNATE
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#undef CONFIG_LID_SWITCH
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#undef CONFIG_CMD_SYSINFO
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#undef CONFIG_CMD_SYSJUMP
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#undef CONFIG_CMD_SYSLOCK
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#ifndef CR50_DEV
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/* Disable stuff that should only be in debug builds */
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#undef CONFIG_CMD_MD
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#undef CONFIG_CMD_RW
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#undef CONFIG_CMD_SLEEPMASK
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#undef CONFIG_CMD_WAITMS
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#undef CONFIG_FLASH
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#endif
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/* Flash configuration */
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#undef CONFIG_FLASH_PSTATE
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/* TODO(crosbug.com/p/44745): Bringup only! Do the right thing for real! */
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#define CONFIG_WP_ALWAYS
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/* TODO(crosbug.com/p/44745): For debugging only */
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#define CONFIG_CMD_FLASH
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/* We're using TOP_A for partition 0, TOP_B for partition 1 */
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#define CONFIG_FLASH_NVMEM
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/* Offset to start of NvMem area from base of flash */
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#define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF)
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#define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF)
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/* Address of start of Nvmem area */
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#define CONFIG_FLASH_NVMEM_BASE_A (CONFIG_PROGRAM_MEMORY_BASE + \
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CONFIG_FLASH_NVMEM_OFFSET_A)
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#define CONFIG_FLASH_NVMEM_BASE_B (CONFIG_PROGRAM_MEMORY_BASE + \
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CONFIG_FLASH_NVMEM_OFFSET_B)
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/* Size partition in NvMem */
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#define NVMEM_PARTITION_SIZE CFG_TOP_SIZE
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/* Size in bytes of NvMem area */
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#define CONFIG_FLASH_NVMEM_SIZE (CFG_TOP_SIZE * NVMEM_NUM_PARTITIONS)
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/* Enable <key, value> variable support. */
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#define CONFIG_FLASH_NVMEM_VARS
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#define NVMEM_CR50_SIZE 272
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#define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE
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/* Allow multiple concurrent memory allocations. */
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#define CONFIG_MALLOC
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/* USB configuration */
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#define CONFIG_USB
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#define CONFIG_USB_CONSOLE
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#define CONFIG_USB_I2C
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#define CONFIG_USB_INHIBIT_INIT
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#define CONFIG_USB_SELECT_PHY
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#define CONFIG_USB_SPI
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#define CONFIG_USB_SERIALNO
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#define DEFAULT_SERIALNO "0"
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#define CONFIG_CMD_GPIO_EXTENDED
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#define CONFIG_STREAM_USART
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#define CONFIG_STREAM_USB
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#define CONFIG_STREAM_USART1
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/* Enable Case Closed Debugging */
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#define CONFIG_CASE_CLOSED_DEBUG
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#define CONFIG_USB_PID 0x502a
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#define CONFIG_USB_SELF_POWERED
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#undef CONFIG_USB_MAXPOWER_MA
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#define CONFIG_USB_MAXPOWER_MA 0
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/* Enable SPI Master (SPI) module */
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#define CONFIG_SPI_MASTER
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#define CONFIG_SPI_MASTER_NO_CS_GPIOS
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#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
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#define CONFIG_SPI_FLASH_PORT 0
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/* We don't need to send events to the AP */
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#undef CONFIG_HOSTCMD_EVENTS
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#define CONFIG_CONSOLE_COMMAND_FLAGS
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/* Include crypto stuff, both software and hardware. */
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#define CONFIG_DCRYPTO
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#define CONFIG_UPTO_SHA512
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#ifndef __ASSEMBLER__
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#include "gpio_signal.h"
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/* USB string indexes */
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enum usb_strings {
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USB_STR_DESC = 0,
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USB_STR_VENDOR,
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USB_STR_PRODUCT,
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USB_STR_VERSION,
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USB_STR_CONSOLE_NAME,
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USB_STR_BLOB_NAME,
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USB_STR_HID_KEYBOARD_NAME,
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USB_STR_AP_NAME,
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USB_STR_UPGRADE_NAME,
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USB_STR_SPI_NAME,
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USB_STR_SERIALNO,
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USB_STR_I2C_NAME,
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USB_STR_COUNT
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};
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void post_reboot_request(void);
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void ccd_force_enable(void);
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void disable_socket(void);
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void enable_socket(void);
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int is_socket_enabled(void);
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int is_socket_off(void);
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#endif /* !__ASSEMBLER__ */
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/* USB interface indexes (use define rather than enum to expand them) */
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#define USB_IFACE_CONSOLE 0
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#define USB_IFACE_AP 1
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#define USB_IFACE_UPGRADE 2
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#define USB_IFACE_SPI 3
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#define USB_IFACE_I2C 4
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#define USB_IFACE_COUNT 5
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/* USB endpoint indexes (use define rather than enum to expand them) */
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#define USB_EP_CONTROL 0
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#define USB_EP_CONSOLE 1
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#define USB_EP_AP 2
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#define USB_EP_UPGRADE 3
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#define USB_EP_SPI 4
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#define USB_EP_I2C 5
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#define USB_EP_COUNT 6
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/* UART indexes (use define rather than enum to expand them) */
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#define UART_CR50 0
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#define UART_AP 1
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#define UARTN UART_CR50
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/* TODO(crosbug.com/p/56540): Remove this when UART0_RX works everywhere */
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#define GC_UART0_RX_DISABLE
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#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_TPM))
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/* Nv Memory users */
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#ifndef __ASSEMBLER__
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enum nvmem_users {
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NVMEM_CR50 = 0,
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NVMEM_NUM_USERS
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};
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#endif
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#define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50
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/*
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* Let's be on the lookout for stack overflow, while debugging.
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*
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* TODO(vbendeb): remove this before finalizing the code.
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*/
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#define CONFIG_DEBUG_STACK_OVERFLOW
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#define CONFIG_RW_B
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/* Firmware upgrade options. */
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#define CONFIG_NON_HC_FW_UPDATE
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#define CONFIG_USB_FW_UPDATE
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#define CONFIG_I2C
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#define CONFIG_I2C_MASTER
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#define I2C_PORT_MASTER 0
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#define CONFIG_INA231
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#endif /* __CROS_EC_BOARD_H */
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