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598d580a63
This change includes - Configuring the HPET timer based on the spec (IA-PC HPET (High Precision Event Timers) Specification 1.0a) - Two timers used: HPET Timer0 (free running periodic timer) HPET Timer1 (event based non-periodic timer) - HPET interrupts are routed to ISH via IOAPIC - Both the timers are functional BUG=None BRANCH=None TEST=`Build ISH and verify the timer interrupt via various console cmds` Change-Id: Ib5ca24d05790868430a2cfa72ca73f5bd6a5fea3 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/453858 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
69 lines
2.0 KiB
C
69 lines
2.0 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_HPET_H
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#define __CROS_EC_HPET_H
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#include "common.h"
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/* ISH HPET config and timer registers */
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#define GENERAL_CAPS_ID_REG 0x00
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#define GENERAL_CONFIG_REG 0x10
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#define GENERAL_INT_STAT_REG 0x20
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#define MAIN_COUNTER_REG 0xF0
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#define TIMER0_CONF_CAP_REG 0x100
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#define TIMER0_COMP_VAL_REG 0x108
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#define TIMER0_FSB_IR_REG 0x110
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#define TIMER1_CONF_CAP_REG 0x120
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#define TIMER1_COMP_VAL_REG 0x128
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#define TIMER1_FSB_IR_REG 0x130
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#define TIMER2_CONF_CAP_REG 0x140
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#define TIMER2_COMP_VAL_REG 0x148
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#define TIMER2_FSB_IR_REG 0x150
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/* ISH 4: Special status register
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* Use this register to see HPET timer are settled after a write.
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*/
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#define CONTROL_AND_STATUS_REG 0x160
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#define HPET_T_CONF_CAP_BIT 0x4
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#define HPET_ENABLE_CNF (1<<0)
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#define HPET_Tn_INT_TYPE_CNF (1<<1)
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#define HPET_Tn_INT_ENB_CNF (1<<2)
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#define HPET_Tn_TYPE_CNF (1<<3)
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#define HPET_Tn_VAL_SET_CNF (1<<6)
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#define HPET_Tn_32MODE_CNF (1<<8)
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#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9
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#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9)
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#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + GENERAL_CONFIG_REG)
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#define HPET_MAIN_COUNTER REG32(ISH_HPET_BASE + MAIN_COUNTER_REG)
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#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + GENERAL_INT_STAT_REG)
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#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + CONTROL_AND_STATUS_REG)
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#define HPET_TIMER_CONF_CAP(x) \
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REG32(ISH_HPET_BASE + TIMER0_CONF_CAP_REG + (x * 0x20))
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#define HPET_TIMER_COMP(x) \
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REG32(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + (x * 0x20))
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#if defined CONFIG_ISH_20
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#define ISH_HPET_CLK_FREQ 1000000 /* 1 MHz clock */
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#elif defined CONFIG_ISH_30
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#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */
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#elif defined CONFIG_ISH_40
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#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */
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#endif
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/* HPET timer 0 period of 10ms (100 ticks per second) */
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#define ISH_TICKS_PER_SEC 100
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#endif /* __CROS_EC_HPET_H */
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